Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

ID 813955
Date 7/26/2024
Public
Document Table of Contents

3.4.2.3. LPDDR4 Interfaces

The following table shows the maximum number of LPDDR4 interfaces per device.

Table 11.  LPDDR4
Package Number of HSIO Banks HSIO Pins Count Avalon® Streaming Interface x16 Support LPDDR4 x32 LPDDR4 x16
B15A 1 62 No 1
Yes

B23B

B23A

1 96 No 1 2
Yes 1

M16A

B23B

B32A

2 192 No 2 4
Yes 1 3
B32A 4 384 No 4 8
Yes 3 7
Note: These values correspond to Fabric EMIF instances.