Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

ID 813955
Date 7/26/2024
Public
Document Table of Contents

3.4.2.2. DDR5 Interfaces

The following table shows the maximum number of DDR55 interfaces per device, with different interface widths.

Table 10.  DDR5
Package Number of HSIO Banks HSIO Pins Count Avalon® Streaming Interface x16 Support DDR5 x40 (x32 + ECC) DDR5 x32 DDR5 x24 DDR5 x16
B23A 1 96 No 1 1 1 2
Yes 1
B32A 2 192 No 2 2 2 4
Yes 1 1 1 3
B32A 4 384 No 4 4 4 8
Yes 3 3 3 7
Note: These values correspond to Fabric EMIF instances.
5 Only supported in Device Group A.