Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

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ID 813955
Date 7/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Migration Scope 3. Functional Area 4. Quartus® Prime Software Design Migration 5. Document Revision History for Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series
2. Migration Scope x
2.1. Migration Supported Packages 2.2. Migration Scenarios 2.3. Considerations for Migration Planning
2.2. Migration Scenarios x
2.2.1. Vertical Migration 2.2.2. Conditional Migration
2.3. Considerations for Migration Planning x
2.3.1. Package B15A 2.3.2. Package M16A 2.3.3. Package B18A 2.3.4. Package B23B 2.3.5. Package B23A 2.3.6. Package B32A
3. Functional Area x
3.1. I/O 3.2. LVDS SERDES 3.3. Configuration 3.4. External Memory Interface 3.5. MIPI D-PHY 3.6. HPS 3.7. Transceiver 3.8. Power 3.9. Sensor
3.1. I/O x
3.1.1. HSIO 3.1.2. HVIO
3.1.1. HSIO x
3.1.1.1. I/O Supply Consideration 3.1.1.2. HSIO Bank Count
3.1.2. HVIO x
3.1.2.1. I/O Supply Consideration 3.1.2.2. HVIO Bank Count
3.4. External Memory Interface x
3.4.1. External Memory Protocol Supported in Agilex™ 5 E-Series Devices 3.4.2. External Memory Interface Support 3.4.3. External Memory Interface Migration Consideration
3.4.2. External Memory Interface Support x
3.4.2.1. DDR4 Interfaces 3.4.2.2. DDR5 Interfaces 3.4.2.3. LPDDR4 Interfaces 3.4.2.4. LPDDR5 Interfaces
3.7. Transceiver x
3.7.1. Migration Overview for Transceiver Application 3.7.2. GTS Transceiver Bank Name Change between Device Variant 3.7.3. GTS Transceiver Resources Count 3.7.4. Pre-planning the board Design for Migration Support 3.7.5. Preserving Unused PMA Lanes
3.7.3. GTS Transceiver Resources Count x
3.7.3.1. Transceiver Lane Count 3.7.3.2. GTS Transceiver Hard IP Block Count 3.7.3.3. USB3.1 Hard IP 3.7.3.4. PERST Pin and HVIO REFCLK Pin 3.7.3.5. CVP Requirement 3.7.3.6. GTS Transmitter (TX) and GTS Receiver (RX) pin, Reference Clock Pin, and RCOMP Pins 3.7.3.7. System PLL in Downbonded Quads
3.7.3.6. GTS Transmitter (TX) and GTS Receiver (RX) pin, Reference Clock Pin, and RCOMP Pins x
3.7.3.6.1. GTS TX and GTS RX pin, and Reference Clock Pin 3.7.3.6.2. RCOMP_GTS Pins
3.7.4. Pre-planning the board Design for Migration Support x
3.7.4.1. CDR Clock Output Pin for Multi and Single Transceiver Banks per Side Device 3.7.4.2. HVIO PLL as Secondary System PLL
3.8. Power x
3.8.1. Power Rails for Migration 3.8.2. Voltage Regulator Considerations for Agilex™ 5 Migration
3.9. Sensor x
3.9.1. Temperature Sensor Location Support
4. Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for Agilex™ 5 E-Series Devices
1. Introduction
2. Migration Scope
3. Functional Area
4. Quartus® Prime Software Design Migration
5. Document Revision History for Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

4.1. Migration via Migration GUI for Agilex™ 5 E-Series Devices

The example design used in this migration is a basic design to address the pin assignment and the I/O standard issues.

  1. To start the device migration, right-click on the device tab in the Project Navigator window. This will navigate you to a pop-up window as shown in the following figure.
    Figure 14. Device Page
  2. Instead of changing the device directly (which will allow the Quartus® Prime software to migrate to a new device by removing all the location assignments), select the Migration Devices tab located at the bottom right of the window as shown in Device Page. When you select the Migration Devices tab, a pop-up window will appear as shown in the following example figure.
    Figure 15. Migration Devices
  3. In the Migration Devices dialog box, click on the arrow buttons to move the migration devices between the Compatible migration devices list and the Selected migration devices list.
    Compatible devices are listed in the Compatible migration devices list. If you want the Quartus® Prime software to display all compatible migration devices in the Compatible migration devices list regardless of a migration device's speed grade, turn on the Show all speed grades option. If you want the Quartus® Prime software to display only the compatible migration devices that have the same speed grade as the target device in the Compatible migration devices list, uncheck the Show all speed grades option.
  4. After choosing the device for migration, click OK. If you do not specify at least one migration device in the Migration Devices dialog box, the field next to Migration Devices tab in the Device window displays 0 migration devices selected.
  5. After specifying the device to use as a migration device, compile the design. However, the device migration may cause additional constraints. Compilation may fail due to the additional constraints, and the errors prompt you to check the pin assignments in the Pin Planner as shown in the following figure.
    Figure 16. Pin Planner
  6. For the non-migratable I/O pins, leave them as NC. You can set the unused I/O pins as input tri-state in the Intel Quartus Prime software.

    Go to Device from the Project Navigator window and click on Devices and Pin Options as shown in the following figure. In the Devices and Pin Options window, under the Reserve all unused pins drop-down list, select As input tri-stated.

    Figure 17. Device Page
    Figure 18. Devices and Pin Options
  7. Remove the location assignment of the non-migratable pins as shown in the following figure and compile the design.
    Figure 19. Location Assignment
    Figure 20. Design Compilation
  8. If you have the flexibility of changing the non-migratable pins and their I/O standards, you can go the Pin Migration View window and check the pins compatibility and assign the pins accordingly.
  9. The Pin Migration View window provides information about the suitability of the pins for device migration, as shown in the following figure. You can open this window in the Pin Planner by clicking View > Pin Migration View. Select a pin in this view to display the following pin migration information:
    • Pin number
    • Migration result
    • Migration devices

    You can access the following commands by right-clicking on the Pin Migration View window in the Pin Planner:

    • Device
    • Pin Finder
    • Show Only Highlighted Pins
    • Show Migration Differences
    • Export
    • Show Columns
    Figure 21. Pin Migration View

    You can look in the Pin Finder to find the pins according to the requirement as shown in the following figure.

    Figure 22. Pin Finder
  10. Change the pin assignment in the Pin Planner as shown in the following figure and compile the design to achieve a successful compilation.
    Figure 23. Pin Assignments
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