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3.4.2.1. DDR4 Interfaces
The following table shows the maximum number of DDR4 interfaces per device, with different interface widths, for both 3 I/O lanes and 4 I/O lanes address/command schemes.
Package | Number of HSIO Banks | HSIO Pins Count | Avalon® Streaming Interface x16 Support | DDR4 x32 + ECC | DDR4 x32 | DDR4 x32 | DDR4 x16 + ECC | DDR4 x16 + ECC | DDR4 x16 | DDR4 x16 |
---|---|---|---|---|---|---|---|---|---|---|
(3AC) | (3AC) | (4AC) | (3AC) | (4AC) | (3AC) | (4AC) | ||||
B15A | 1 | 62 | Yes | – | – | – | – | – | – | – |
No | – | – | – | – | – | 1 | – | |||
B23B B23A |
1 | 96 | No | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Yes | – | – | – | – | – | – | – | |||
M16A B23B B32A |
2 | 192 | No | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
Yes | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
B32A | 4 | 384 | No | 4 | 4 | 4 | 4 | 4 | 4 | 4 |
Yes | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
Note: These values correspond to Fabric EMIF instances.