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3.3. Configuration
All Agilex™ 5 E-Series devices that are designed with the PCIe HIP block located on the left side of the device support the Configuration via Protocol (CvP) application except for A5E005B and A5E007B devices, which are not designed with PCIe HIP. The device that supports the CvP application supports migration within the same package across different devices. Refer all the package diagram documented in section 2.3 for more details about the product line that supports CvP application.
Refer to the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs and the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs for more details on configuration solutions for Agilex™ 5 E-Series devices.
- HSIO – High-speed I/O
- HVIO – High voltage I/O
- LVDS – Low voltage differential signaling channels