Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

ID 813955
Date 7/26/2024
Public
Document Table of Contents

3.7.4.1. CDR Clock Output Pin for Multi and Single Transceiver Banks per Side Device

If you are planning to migrate from bigger device variant to a smaller device variant that only supports a single GTS transceiver bank on either the left or right side of the device, then you need to bond out the CDR clock output (CDRCLKOUT_GTS) pin on the bigger density device instead to allow migration to smaller device variant.

If you do not plan to migrate to a smaller device family with a single transceiver bank on either the left or right side, you can optionally route the CDR clock output pin to the local reference clock pin in the same bank.