Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

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ID 813955
Date 7/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Migration Scope 3. Functional Area 4. Quartus® Prime Software Design Migration 5. Document Revision History for Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series
2. Migration Scope x
2.1. Migration Supported Packages 2.2. Migration Scenarios 2.3. Considerations for Migration Planning
2.2. Migration Scenarios x
2.2.1. Vertical Migration 2.2.2. Conditional Migration
2.3. Considerations for Migration Planning x
2.3.1. Package B15A 2.3.2. Package M16A 2.3.3. Package B18A 2.3.4. Package B23B 2.3.5. Package B23A 2.3.6. Package B32A
3. Functional Area x
3.1. I/O 3.2. LVDS SERDES 3.3. Configuration 3.4. External Memory Interface 3.5. MIPI D-PHY 3.6. HPS 3.7. Transceiver 3.8. Power 3.9. Sensor
3.1. I/O x
3.1.1. HSIO 3.1.2. HVIO
3.1.1. HSIO x
3.1.1.1. I/O Supply Consideration 3.1.1.2. HSIO Bank Count
3.1.2. HVIO x
3.1.2.1. I/O Supply Consideration 3.1.2.2. HVIO Bank Count
3.4. External Memory Interface x
3.4.1. External Memory Protocol Supported in Agilex™ 5 E-Series Devices 3.4.2. External Memory Interface Support 3.4.3. External Memory Interface Migration Consideration
3.4.2. External Memory Interface Support x
3.4.2.1. DDR4 Interfaces 3.4.2.2. DDR5 Interfaces 3.4.2.3. LPDDR4 Interfaces 3.4.2.4. LPDDR5 Interfaces
3.7. Transceiver x
3.7.1. Migration Overview for Transceiver Application 3.7.2. GTS Transceiver Bank Name Change between Device Variant 3.7.3. GTS Transceiver Resources Count 3.7.4. Pre-planning the board Design for Migration Support 3.7.5. Preserving Unused PMA Lanes
3.7.3. GTS Transceiver Resources Count x
3.7.3.1. Transceiver Lane Count 3.7.3.2. GTS Transceiver Hard IP Block Count 3.7.3.3. USB3.1 Hard IP 3.7.3.4. PERST Pin and HVIO REFCLK Pin 3.7.3.5. CVP Requirement 3.7.3.6. GTS Transmitter (TX) and GTS Receiver (RX) pin, Reference Clock Pin, and RCOMP Pins 3.7.3.7. System PLL in Downbonded Quads
3.7.3.6. GTS Transmitter (TX) and GTS Receiver (RX) pin, Reference Clock Pin, and RCOMP Pins x
3.7.3.6.1. GTS TX and GTS RX pin, and Reference Clock Pin 3.7.3.6.2. RCOMP_GTS Pins
3.7.4. Pre-planning the board Design for Migration Support x
3.7.4.1. CDR Clock Output Pin for Multi and Single Transceiver Banks per Side Device 3.7.4.2. HVIO PLL as Secondary System PLL
3.8. Power x
3.8.1. Power Rails for Migration 3.8.2. Voltage Regulator Considerations for Agilex™ 5 Migration
3.9. Sensor x
3.9.1. Temperature Sensor Location Support
4. Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for Agilex™ 5 E-Series Devices
1. Introduction
2. Migration Scope
3. Functional Area
4. Quartus® Prime Software Design Migration
5. Document Revision History for Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

3.5. MIPI D-PHY

Agilex™ 5 E-Series package B15A, M16A, and B23A have the same number of HSIO counts. You can migrate the MIPI D-PHY design within the package with the same number of HSIO bank counts.

Agilex™ 5 E-Series package B23B and B32A include devices with different HSIO counts. When you are migrating from a device with smaller HSIO counts to bigger HSIO counts, you can reuse the MIPI D-PHY Link.

Considerations must be taken when you are migrating from bigger HSIO count devices to smaller HSIO count devices. You can only utilize the HSIO count of the smaller device to determine the maximum number of MIPI D-PHY Link that can be supported.

Refer to the migration path for Agilex™ 5 E-Series devices in the Considerations for Migration Planning section.

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