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1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
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6.1.2.5. Multiport MAC FIFO Status Signals
The MAC FIFO status interface is an Avalon streaming sink port which streams in information on the fill level of the external FIFO buffer to the MAC function.
Signal Name | Avalon Streaming Signal Type | I/O | Description |
---|---|---|---|
rx_afull_valid_n | valid | I | Assert this signal to indicate that the fill level of the external FIFO buffer, rx_afull_data_n[1:0], is valid. |
rx_afull_data_n[1:0] | data | I | Carries the fill level of the external FIFO buffer: rx_afull_data_n[1]—Set to 1 if the external receive FIFO buffer reaches the initial warning level indicating that it is almost full. Upon detecting this, the MAC function generates pause frames. rx_afull_data_n[0]—Set to 1 if the external receive FIFO buffer reaches the critical level before it overflows. The FIFO buffer can be considered overflow if this bit is set to 1 in the middle of a packet transfer. |
rx_afull_channel[(CHANNEL_WIDTH-1):0] | channel | I | The port number the status applies to. |
rx_afull_clk | clk | I | The clock that drives the MAC FIFO status interface. |
Interface Signal | Section |
---|---|
Clock and reset signals | Clock and Reset Signals |
MAC control interface | MAC Control Interface Signals |
MAC transmit interface | MAC Transmit Interface Signals |
MAC receive interface | MAC Receive Interface Signals |
Status signals | MAC Status Signals |
Pause and magic packet signals | Pause and Magic Packet Signals |
MII/GMII/RGMII interface | MII/GMII/RGMII Signals |
PHY management signals | PHY Management Signals |