Visible to Intel only — GUID: eix1662616606246
Ixiasoft
Visible to Intel only — GUID: eix1662616606246
Ixiasoft
5.3.2. Triple-Speed Ethernet System with SGMII
Use the following recommended initialization sequences for the example shown in the figure above.
- External PHY Initialization using MDIO
Refer to step 1 in System with MII/GMII.
- PCS Configuration Register Initialization
- Set Auto Negotiation Link Timer
//Set Link timer to 1.6ms for SGMII
link_timer (address offset 0x12) = 0x0D40
Link_timer (address offset 0x13) = 0x03
- Configure SGMII
//Enable SGMII Interface and Enable SGMII Auto Negotiation
//SGMII_ENA = 1, USE_SGMII_AN = 1
if_mode = 0x0003
- Enable Auto Negotiation
//Enable Auto Negotiation
//AUTO_NEGOTIATION_ENA = 1, Bit 6,8,13 can be ignored
PCS Control Register = 0x1140
- PCS Reset
//PCS Software reset is recommended where there any configuration changed
//RESET = 1
PCS Control Register = 0x9140
Wait PCS Control Register RESET bit is clear
- Set Auto Negotiation Link Timer
- MAC Configuration Register Initialization
Refer to step 2 in System with MII/GMII.
If 1000BASE-X/SGMII PCS is initialized, set the ETH_SPEED (bit 3) and ENA_10 (bit 25) in command_config register to 0. If half duplex is reported in the PHY/PCS status register, set the HD_ENA (bit 10) to 1 in command_config register.