Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 4/01/2024
Public

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8. Timing Constraints

Intel provides timing constraint files (.sdc) to ensure that the IP meets the design timing requirements in Intel FPGA devices. The files constraints the false paths and multi-cycle paths in the IP. The timing constraints files are specified in the <variation_name>.qip file and is automatically included in the Quartus® Prime project files.

You may need to add timing constraints that are external to the IP. The following sections describe the procedure to create the timing constraint file.