Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals

Figure 41. 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers with 1000BASE-X/SGMII PCS Signals
Table 62.  References
Interface Signal Section
Clock and reset signals Clock and Reset Signals
MAC control interface signals MAC Control Interface Signals
MAC transmit interface signals MAC Transmit Interface Signals
MAC receive interface signals MAC Receive Interface Signals
MAC packet classification signals Multiport MAC Packet Classification Signals
MAC FIFO status signals Multiport MAC FIFO Status Signals
Pause and magic packet signals Pause and Magic Packet Signals
PHY management signals PHY Management Signals
Ten-bit interface signals TBI Interface Signals
Status LED signals Status LED Control Signals
SERDES control signals SERDES Control Signals