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1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
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9.6.1. Generate the Simulation Model
The generated design example includes both Verilog HDL and VHDL testbench files for the device under test (DUT)—your custom IP variation.
To generate a Verilog functional simulation model, use the command prompt and run the quartus_sh -t generate_sim_verilog.tcl file. Alternatively, perform the following steps:
- Launch the Quartus® Prime software and browse to the <variation name>_testbench directory.
- Open the generate_sim.qpf file from the project directory.
- On the Tools menu, select Tcl Scripts and select the generate_sim_verilog.tcl file.
- Click Run.
To generate a VHDL functional simulation model, you can use the command prompt and run the quartus_sh -t generate_sim_vhdl.tcl file. Alternatively, perform the following steps:
- Launch the Quartus® Prime software and browse to the <variation name>_testbench directory.
- Open the generate_sim.qpf file from the project directory.
- On the Tools menu, select Tcl Scripts and browse to the generate_sim_vhdl.tcl file.
- Click Run.