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1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
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1.3. Features
- Complete Triple-Speed Ethernet: 10/100/1000 Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and embedded PMA (GTS).
- 10/100/1000 Mbps Ethernet MAC features:
- Multiple variations: 10/100/1000 Mbps Ethernet MAC in full duplex, 10/100 Mbps Ethernet MAC in half duplex, 10/100 Mbps or 1000 Mbps small MAC (resource-efficient variant), and multiport MAC that supports up to 24 ports.
- Support for basic, virtual LAN (VLAN), stacked VLAN, and jumbo Ethernet frames. Also supports control frames including pause frames.
- Optional internal FIFO buffers, depth from 64 bytes to 256 Kbytes.
- Optional statistics counters.
- MAC interfaces:
- Client side—8 bit or 32 bit Avalon® streaming interface
- Network side— MII, GMII, or RGMII on the network side. Optional loopback on these interfaces.
- Optional management data input/output (MDIO) master interface for PHY device management.
- 1000BASE-X/SGMII PCS features:
- Compliance with Clause 36 of the IEEE standard 802.3.
- Embedded PMA (GTS) implemented with serial transceiver in Intel FPGA devices that support this interface at 1.25 Gbps data rate.
- Support for auto-negotiation as defined in Clause 37.
- Support for connection to 1000BASE-X PHYs. Support for 10BASE-T, 100BASE-T, and 1000BASE-T PHYs if the PHYs support SGMII.
- PCS interfaces:
- Client side—MII or GMII
- Network side—ten-bit interface (TBI) for PCS without PMA; 1.25 Gbps serial interface for PCS with PMA implemented with serial transceiver in Intel FPGA devices that support this interface at 1.25 Gbps data rate.
- Programmable features via 32 bit configuration registers:
- FIFO buffer thresholds.
- Pause quanta for flow control.
- Source and destination MAC addresses.
- Address filtering on receive, up to 5 unicast and 64 multicast MAC addresses.
- Promiscuous mode—receive frame filtering is disabled in this mode.
- Frame length—in MAC only variation, up to 64 Kbytes including jumbo frames. In all variants containing 1000BASE-X/SGMII PCS (with or without MAC), the frame length is up to 10 Kbytes.
- Optional auto-negotiation for the 1000BASE-X/SGMII PCS.