Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 4/01/2024
Public

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2.4.1. Design Constraint File

The following table lists the recommended Quartus® Prime pin assignments that you can set in your design.

Table 8.  Recommended Quartus® Prime Pin Assignments
Pin Assignment Assignment Value Description Design Pin
FAST_INPUT_REGISTER ON To optimize I/O timing for MII, GMII and TBI interface. MII, GMII, RGMII, TBI input pins.
FAST_OUTPUT_REGISTER ON To optimize I/O timing for MII, GMII and TBI interface. MII, GMII, RGMII, TBI output pins.
IO_STANDARD High Speed Differential I/O

I/O standard for GTS serial input and output pins.

GTS transceiver serial input and output pins.

GLOBAL_SIGNAL Global clock To assign clock signals to use the global clock network. Use this setting to guide the Quartus® Prime software in the fitter process for better timing closure.
  • clk and reset pins for MAC only (without internal FIFO).
  • clk and reference clocks input pins for MAC and PCS with transceiver (without internal FIFO).
GLOBAL_SIGNAL Regional clock To assign clock signals to use the regional clock network. Use this setting to guide the Quartus® Prime software in the fitter process for better timing closure.
  • rx_clk <n> and tx_clk <n> input pins for MAC only using MII/GMII interface (without internal FIFO).