Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 4/01/2024
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6.1.1.8. MII/GMII/RGMII Signals

Table 47.  GMII/RGMII/MII Signals
Name I/O Description
GMII Transmit
gm_tx_d[7:0] I GMII transmit data bus.
gm_tx_en O Asserted to indicate that the data on the GMII transmit data bus is valid.
gm_tx_err O Asserted to indicate to the PHY that the frame sent is invalid.
GMII Receive
gm_rx_d[7:0] I GMII receive data bus.
gm_rx_dv I Assert this signal to indicate that the data on the GMII receive data bus is valid. Keep this signal asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received.
gm_rx_err I The PHY asserts this signal to indicate that the receive frame contains errors.
RGMII Transmit
rgmii_out[3:0] O
RGMII transmit data bus.
  • In 1000M speed mode: Drives rgmii_out[3:0] on both edges of rgmii_tx_clk.
  • In 10M and 100M speed mode: Drives rgmii_out[3:0] on the positive edge of rgmii_tx_clk.
tx_control O RGMII control output signal. Drives gm_tx_en on the positive edge of rgmii_tx_clk and a logical derivative of (gm_tx_en XOR gm_tx_err) on the negative edge of rgmii_tx_clk .
RGMII Receive
rgmii_in[3:0] I
RGMII receive data bus.
  • In 1000M speed mode: Drives on both edges of rgmii_rx_clk.
  • In 10M and 100M speed mode: Drives on the positive edge of rgmii_rx_clk.
rx_control I RGMII control input signal. Expects gm_rx_dv on the positive edge of rgmii_rx_clk and a logical derivative of (gm_rx_dv XOR gm_rx_err) on the negative edge of rgmii_tx_clk .
RGMII Clocks
rgmii_tx_clk O RGMII transmit interface clock with frequencies 2.5/25/125 MHz for 10/100/1000M speed modes respectively.
rgmii_rx_clk I RGMII receive interface clock with frequencies 2.5/25/125 MHz for 10/100/1000M speed modes respectively. This is the recovered clock from external PHY module.
MII Transmit
m_tx_d[3:0] O MII transmit data bus.
m_tx_en O Asserted to indicate that the data on the MII transmit data bus is valid.
m_tx_err O Asserted to indicate to the PHY device that the frame sent is invalid.
MII Receive
m_rx_d[3:0] I MII receive data bus.
m_rx_en I Assert this signal to indicate that the data on the MII receive data bus is valid. Keep this signal asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received.
m_rx_err I The PHY asserts this signal to Indicate that the receive frame contains errors.
MII PHY Status
m_rx_col I Collision detection. The PHY asserts this signal to indicate a collision during frame transmission. This signal is not used in full- duplex or gigabit mode.
m_rx_crs I Carrier sense detection. The PHY asserts this signal to indicate that it has detected transmit or receive activity on the Ethernet line. This signal is not used in full-duplex or gigabit mode.