Visible to Intel only — GUID: bhc1410931975453
Ixiasoft
Visible to Intel only — GUID: bhc1410931975453
Ixiasoft
5.3.1. Triple-Speed Ethernet System with MII/GMII or RGMII
Use the following recommended initialization sequences for the example shown in the figure above.
- External PHY Initialization using MDIO
//Assume the External PHY Address is 0x0A
mdio_addr0 = 0x0A
//External PHY Register will Map to MDIO Space 0
Read/write to MDIO space 0 (dword offset 0x80 - 0x9F) = Read/write to PHY Register 0 to 31
- MAC Configuration Register Initialization
- Disable MAC Transmit and Receive Datapath Disable the MAC transmit and receive datapath before performing any changes to configuration.
//Set TX_ENA and RX_ENA bit to 0 in Command Config Register
Command_config Register = 0x00802220
//Read the TX_ENA and RX_ENA bit is set 0 to ensure TX and RX path is disable
Wait Command_config Register = 0x00802220
- MAC FIFO Configuration
Tx_section_empty = Max FIFO size - 16
Tx_almost_full = 3
Tx_almost_empty = 8
Rx_section_empty = Max FIFO size - 16
Rx_almost_full = 8
Rx_almost_empty = 8
//Cut Through Mode, Set this Threshold to 0 to enable Store and Forward Mode
Tx_section_full = 16
//Cut Through Mode, Set this Threshold to 0 to enable Store and Forward Mode
Rx_section_full = 16
- MAC Address Configuration
//MAC address is 00-1C-23-17-4A-CB
mac_0 = 0x17231C00
mac_1 = 0x0000CB4A
- MAC Function Configuration
//Maximum Frame Length is 1518 bytes
Frm_length = 1518
//Minimum Inter Packet Gap is 12 bytes
Tx_ipg_length = 12
//Maximum Pause Quanta Value for Flow Control
Pause_quant = 0xFFFF
//Set the MAC with the following option:
// 100Mbps, User can get this information from the PHY status/PCS status
//Full Duplex, User can get this information from the PHY status/PCS status
//Padding Removal on Receive
//CRC Removal
//TX MAC Address Insertion on Transmit Packet
//Select mac_0 and mac_1 as the source MAC Address
Command_config Register = 0x00800220
- Reset MAC
Intel recommends that you perform a software reset when there is a change in the MAC speed or duplex. The MAC software reset bit self-clears when the software reset is complete.
//Set SW_RESET bit to 1
Command_config Register = 0x00802220
Wait Command_config Register = 0x00800220
- Enable MAC Transmit and Receive Datapath
//Set TX_ENA and RX_ENA to 1 in Command Config Register
Command_config Register = 0x00800223
//Read the TX_ENA and RX_ENA bit is set 1 to ensure TX and RX path is enable
Wait Command_config Register = 0x00800223
- Disable MAC Transmit and Receive Datapath Disable the MAC transmit and receive datapath before performing any changes to configuration.