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1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
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6.1.1.8. MII/GMII/RGMII Signals
Name | I/O | Description |
---|---|---|
GMII Transmit | ||
gm_tx_d[7:0] | I | GMII transmit data bus. |
gm_tx_en | O | Asserted to indicate that the data on the GMII transmit data bus is valid. |
gm_tx_err | O | Asserted to indicate to the PHY that the frame sent is invalid. |
GMII Receive | ||
gm_rx_d[7:0] | I | GMII receive data bus. |
gm_rx_dv | I | Assert this signal to indicate that the data on the GMII receive data bus is valid. Keep this signal asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received. |
gm_rx_err | I | The PHY asserts this signal to indicate that the receive frame contains errors. |
RGMII Transmit | ||
rgmii_out[3:0] | O |
RGMII transmit data bus.
|
tx_control | O | RGMII control output signal. Drives gm_tx_en on the positive edge of rgmii_tx_clk and a logical derivative of (gm_tx_en XOR gm_tx_err) on the negative edge of rgmii_tx_clk . |
RGMII Receive | ||
rgmii_in[3:0] | I |
RGMII receive data bus.
|
rx_control | I | RGMII control input signal. Expects gm_rx_dv on the positive edge of rgmii_rx_clk and a logical derivative of (gm_rx_dv XOR gm_rx_err) on the negative edge of rgmii_tx_clk . |
RGMII Clocks | ||
rgmii_tx_clk | O | RGMII transmit interface clock with frequencies 2.5/25/125 MHz for 10/100/1000M speed modes respectively. |
rgmii_rx_clk | I | RGMII receive interface clock with frequencies 2.5/25/125 MHz for 10/100/1000M speed modes respectively. This is the recovered clock from external PHY module. |
MII Transmit | ||
m_tx_d[3:0] | O | MII transmit data bus. |
m_tx_en | O | Asserted to indicate that the data on the MII transmit data bus is valid. |
m_tx_err | O | Asserted to indicate to the PHY device that the frame sent is invalid. |
MII Receive | ||
m_rx_d[3:0] | I | MII receive data bus. |
m_rx_en | I | Assert this signal to indicate that the data on the MII receive data bus is valid. Keep this signal asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received. |
m_rx_err | I | The PHY asserts this signal to Indicate that the receive frame contains errors. |
MII PHY Status | ||
m_rx_col | I | Collision detection. The PHY asserts this signal to indicate a collision during frame transmission. This signal is not used in full- duplex or gigabit mode. |
m_rx_crs | I | Carrier sense detection. The PHY asserts this signal to indicate that it has detected transmit or receive activity on the Ethernet line. This signal is not used in full-duplex or gigabit mode. |