AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

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ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

4.11. Planning NoC and Memory Solution Clocks

The Intel Agilex® 7 M-Series FPGA device architecture offers a variety of clocking schemes. Understanding these clocking schemes for your application allows you to plan and optimize clocking usage for the best performance.

Well informed planning and placement of each clock domain can improve system level performance.

The hard memory NoC, memory Intel FPGA IP, and associated features provide:

  • Solutions for efficient clock resource utilization
  • Support for an increased number of design clocks
  • Improved clock characteristics for performance and power

This section covers only the clocking alternatives for data flow to and from the FPGA core. This section does not cover reference and PLL clock requirements for the hard memory NoC and memories. You can find more information on these subjects in External Memory Interfaces Intel Agilex 7 M-Series FPGA IP User Guide, High Bandwidth Memory (HBM2E) Interface Intel Agilex 7 FPGA IP User Guide, and Intel Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide.

Summary of Clocking Schemes provides a summary of the available clocking schemes, including the supported frequencies and considerations. The frequency is for a single initiator. For complex designs, the supported frequency depends on your design timing closure.

Table 12.  Summary of Clocking Schemes
Clocking Configuration Read/Write Data Width Write Data Path User Clock (MHz) Read Data Path User Clock (MHz) Considerations
Clocking scheme without fabric NoC 256b - 256b <=660 (-1 speed grade) <=660 (-1 speed grade)
  • Limited read bandwidth.
  • Timing closure difficulties close to maximum allowed frequency for complex design.
  • An area efficient option.
<=630 (-2 speed grade) <=630 (-2 speed grade)
<=450 (-3 speed grade) <=450 (-3 speed grade)
Symmetric data path for both read and write with same clock 512b – 512b >=350 (-1 speed grade)
  • Can saturate HBM read bandwidth for -2 and -3 device speed grade.
  • Uses the Fabric NoC which requires added area utilization in core.
>=350 (-2 speed grade)
>=250 (-3 speed grade)
Asymmetric width read path and write path driven by common clock 512b – 256b >=350 to <= 660 (-1 speed grade)
  • Can saturate read bandwidth.
  • Uses the Fabric NoC which requires additional area utilization in core. You save some area relative to the symmetric clocking scheme because there is no requirement for clock crossing on 512 data paths.
  • Difficult timing closure.
  • Does not require clock crossing in core logic.
>=350 to <= 630 (-2 speed grade)
>=250 to <= 450 (-3 speed grade)
Asymmetric width read path and write path driven by separate clocks 512b – 256b <=660 (-1 speed grade) <=350 (-1 speed grade)
  • Can saturate read bandwidth.
  • Fabric NoC requires additional area utilization in core. You save some area relative to the above clocking scheme because there is no requirement for clock crossing on 512 data paths.
  • Depending on system, additional PLL is required.
  • Easier to close timing due to low frequency on read clock.
  • Write bandwidth is not saturated.
<= 630 (-2 speed grade) >=350 (-2 speed grade)
<= 450 (-3 speed grade) >=250 (-3 speed grade)
Note: In the ‘Symmetric data path for both read and write with the same clock’ clocking scheme, you must supply noc_bridge_fabric_clk through the NoC Initiator IP. This clock supports frequencies up to 660 MHz for -1 device speed grade, up to 630 MHz for -2 device speed grade, and up to 450 MHz for -3 device speed grade.

Section Content
Clocking without the Fabric NoC
Clocking with the Fabric NoC

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