AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

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ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC Symmetrical Data Path Configuration Asymmetric Width Read Path and Write Path Driven by Separate Clocks Asymmetric Width Read and Write Path Clocks Driven by a Common Clock
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

4.11.2. Clocking with the Fabric NoC

The addition of the fabric NoC exposes the following additional clocking schemes:
  • Symmetric data path for both read and write (512-bit wide) with same clock
  • Asymmetric width read path and write path driven by separate clock
  • Asymmetric width read path and write path driven by common clock

Symmetrical Data Path Configuration

In symmetrical data path configuration, the NoC Initiator Intel FPGA IP has a single 512-bit wide AXI interface for both read and write data paths. The fabric NoC feature converts the 256-bit read path from the initiator to a 512-bit read through the fabric NoC async FIFO. Meanwhile, the 256-bit write is also converted to a 512-bit write using the write async FIFO within the NoC Initiator IP.

Figure 11. Symmetrical Data Path Clock Configuration with Fabric NoC


Note: HNoC Clock and HNoC Clock/2 are not exposed.

As Symmetrical Data Path Clock Configuration with Fabric NoC shows, if you configure the NoC initiator for symmetric 512-bit wide AXI4 interfaces, the user core clock (s0_axi4_clk) drives read and write interfaces, and a separate NoC bridge clock (and reset) (noc_bridge_fabric_clk) drives the NoC initiator hardware.

The noc_bridge_fabric_clk is exposed when you choose a 512-bit wide data mode with fabric NoC through the NoC Initiator Intel FPGA IP.

For the allowed range of user core clock and NoC bridge clock, refer to Summary of Clocking Scheme.

As Symmetrical Data Path Clock Configuration with Fabric NoC shows, the HNoC clock always drives the horizontal NoC at a fixed frequency based on your device speed grade.

Asymmetric Width Read Path and Write Path Driven by Separate Clocks

This configuration is similar to the symmetrical configuration, except there are separate read-only and write-only AXI4 interfaces. The read-only interface has a read data width of 512-bit. The write-only interface has write data width of 256 bits.

As Asymmetric Width Read Path and Write Path Driven by Separate Clocks shows, when you configure the NoC Initiator Intel FPGA IP with asymmetric read-write, this exposes two separate s0_ro_axi4_clk (read) and s0_wo_axi4_clk (write) clocks. You can run the 256-bit wide write data path with a faster clock, which would improve write bandwidth. The 256-bit write data path runs at a separate core clock frequency. The NoC bridge clock is internally driven by the write user clock, and does not expose as a separate clock in this clocking scheme.

For the allowed range of user core clock and NoC bridge clock, refer to Summary of Clocking Scheme.

Figure 12. Asymmetric Width Read Path and Write Path Driven by Separate Clocks


Note: HNoC Clock and HNoC Clock/2 are not exposed.

Asymmetric Width Read and Write Path Clocks Driven by a Common Clock

Asymmetric Width Read and Write Path Clocks Driven by a Common Clock is similar to the asymmetrical configuration, except you can tie the two separate clocks for read and write to a common clock source. There is only one clock domain that drives the read and write data path from the user-logic. You can still have separate read-only and write-only AXI4 interfaces where only read-data path is 512-bit wide. The NoC bridge clock is internally driven by the write user clock and is not exposed as separate clock in this clocking scheme. For the permitted range of the user core clock and NoC bridge clock, refer to Summary of Clocking Scheme.

Figure 13. Asymmetric Width Read and Write Path Clocks Driven by a Common Clock


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