AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

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ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

4.10.3. AXI4-Lite Initiator for EMIF

The Intel Agilex 7 M-Series FPGA EMIF architecture supports access to external memory via a hard memory controller, either through the horizontal NoC or in bypass mode. AXI4-Lite is a required interface for EMIF to read the calibration status before launching user traffic.

EMIF supports both the NoC AXI4-Lite interface and fabric AXI4-Lite interface. If the EMIF implementation is in bypass mode, you can only use the fabric AXI4-Lite interface. When the EMIF implementation is through NoC, you can choose either the NoC AXI4-Lite or fabric AXI4-Lite interface.

The following AXI4 Lite options are available:

  • AXI4-Lite access through a dedicated AXI4-Lite initiator
  • AXI4-Lite access through an initiator that is shared with AXI4
  • AXI4-Lite access through Fabric mode

Based on your application’s memory bandwidth needs, which dictate the number of initiators required and memory frequency, you can either choose NoC AXI4-Lite or fabric AXI4-Lite. You can use a dedicated AXI4-Lite initiator for each EMIF on a side of the Hard Memory NoC if your design requires a high bandwidth from AXI Lite. Otherwise, that configuration unnecessarily occupies prime initiator resources for only sideband operations.

Using a dedicated AXI4-Lite initiator for all EMIF IP instances on a side of the hard memory NoC is a better option. Using fabric AXI4-Lite for sideband operations may lead to more congestion, routing, and timing closure challenges in the FPGA core near the horizontal NoC boundary.

The shared initiator between AXI4 and AXI4-Lite option adds a restriction on fabric NoC usage. If your system requires higher read bandwidth and the use of fabric NoC, you cannot use a shared initiator for mainband and sideband operations. You cannot use the fabric NoC with a shared AXI4-Lite option. However, you can still use the fabric NoC with AXI4-Lite in a dedicated option.

For more details on EMIF configuration and status register access by AXI4-Lite, refer to External Memory Interfaces Intel Agilex 7 M-Series FPGA IP User Guide.

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