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1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History
2.1.3.1. Boot-To-Operating System Prompt
2.1.3.2. Basic Ethernet
2.1.3.3. CPU Power-On and Boot Core Selection
2.1.3.4. Reset Flow
2.1.3.5. General Purpose I/O (GPIO) Loopback
2.1.3.6. USB Disks Hot-Plug Support
2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design
2.1.3.8. FPGA-to-HPS Bridges
2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design
2.1.3.10. USB Controller Host/Device Mode Configuration
2.1.3.11. B0 Silicon Features Selection
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2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview
The Agilex™ 5 E-Series universal virtual platform provides a virtual GHRD running in an FPGA-first boot configuration. The simulation enabled by the virtual platform starts after the device configuration is complete, and the device is in user mode.
This virtual platform is associated with the agilex5e-universal.simics target script.
Use the virtual platform to exercise your embedded software binaries in a simulation without needing physical hardware. In the simulation, you can run the same embedded software binaries that you run on hardware. No changes are required to the binaries to run them in the simulation.
This virtual platform is called a universal virtual platform because you can use all the modeled peripherals in the Agilex™ 5 E-Series HPS in your Intel® Simics® simulation. In hardware, the number and types of peripherals you can use are restricted due to constraints imposed by some components like pin multiplexing (pinmux) or combination physical layer interfaces (combo PHY).
With pin multiplexing, only a subset of peripherals can be enabled simultaneously physical hardware because there are not enough physical pins available to enable all peripherals. In an Intel® Simics® simulation environment, the physical constraints can be relaxed so that all peripherals can be enabled simultaneously.
In the physical hardware for the combo PHY, signals can be sent to the multiplexed pins (either NAND or SDMMC) for only one flash controller at a time. In the virtual platform, you can have separate ports for each controller, and you can have both controllers enabled simultaneously.
The following diagram shows a high-level block diagram of the virtual platform. The hierarchical architecture of the virtual platform is indicated by the larger boxes that enclose combinations of various components.
The larger blocks in this diagram (HPS, HPS subsystem, soc_inst, FPGA, Board, System, and target script) are described in the following sections.
Figure 1. High-level Block Diagram of the Agilex™ 5 E-Series Universal Virtual Platform