Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

ID 786901
Date 8/08/2024
Public
Document Table of Contents

2.1.2. Agilex™ 5 E-Series Universal Virtual Platform User-Configurable Parameters

The Agilex™ 5 E-Series Universal Virtual Platform has the following user-configurable parameters provided in the target script:

Table 7.   Agilex™ 5 E-Series Universal Virtual Platform Parameters
Parameter Description
create_hps_eth0_network

Create a basic Ethernet network and connect it to the eth0 peripheral of the Hard Processor System Agilex™ 5 FPGA IP.

  • Range: Boolean
  • Default value: True
create_hps_sd_card

Create the SD card in the board component and connect it to the SD/eMMC controller. You can set either the create_hps_sd_card or create_hps_mmc parameter to true at a time.

  • Range: Boolean
  • Default value: True
create_hps_mmc

Create the eMMC card in the board component and connect it to the SD/eMMC controller. You can set either the create_hps_sd_card or create_hps_mmc parameter to true at a time.

  • Range: Boolean
  • Default value: False
create_hps_serial0_console

Create a console component and connect it to the serial0 peripheral of the Hard Processor System Agilex™ 5 FPGA IP.

  • Range: Boolean
  • Default value: True
fsbl_image_filename

First stage bootloader file. Supported format is .bin .

  • Range: File name string.
  • Default value: ""
hps_boot_core

The CPU to use as the boot core.

  • Range: Integer: [0,2]
  • Default value: 0
hps_core0_1_power_on

The power-on states of CPU 0/1.

  • Range: Boolean
  • Default value: True
hps_core2_power_on

The power-on state of CPU 2.

  • Range: Boolean
  • Default value: True
hps_core3_power_on

The power-on state of CPU 3.

  • Range: Boolean
  • Default value: True
sd_image_filename

Name of the SD image to load into the SD memory model of the board component. The supported format is .craff, .img, or .wic.

  • Range: File name string.
  • Default value: ""
nand_data_image_filename

Name of the NAND image to load into the NAND memory model of the board component. The supported format is raw binary (.bin or .craff).

  • Range: File name string.
  • Default value: ""
nand_spare_image_filename

Name of the NAND spare image to load into the NAND memory model of the board component. The supported format is raw binary (.bin or .craff).

  • Range: File name string.
  • Default value: ""
qspi_image_filename

Name of the QSPI image to load into the QSPI memory model of the board component. The supported format is raw binary (.bin or .craff).

  • Range: File name string.
  • Default value: ""
usb3_image_filename

Name of the USB disk image that corresponds to the usb3_disk (SuperSpeed disk) in the board component. The image file must be smaller or equal than the disk size.

The supported format is .craff, .img or .wic.

  • Range: File name string.
  • Default value: ""
Note: usb3_disk is connected to usb1_typec port when a valid image file is provided by this parameter.
usb3_hs_image_filename

Name of the USB disk image that corresponds to the usb3_hs_disk (high-speed disk) in the board component. The image file must be smaller or equal than the disk size.

The supported format is .craff, .img or .wic.

  • Range: File name string.
  • Default value: ""
Note: usb3_hs_disk is connected to usb1_typec port if a valid image file is provided through the usb3_hs_image_filename parameter and usb1_typec port is available (when a valid image file is not provided in the usb3_image_filename parameter).
usb_otg_image_filename

Name of the USB disk image that corresponds to the usbotg_disk (high-speed disk) in the board component. The image file must be smaller or equal than the disk size.

The supported format is .craff, .img or .wic.

  • Range: File name string.
  • Default value: ""
Note: The usbotg_disk is connected to the usb0_otg port when a valid image file is provided by this parameter.
hps_cpu_freq_mhz ARM cores frequency in Megahertz (MHz).
  • Range: Integer between 400 and 1500
  • Default value: 400 MHz
stepping Select the silicon features that the Agilex™ 5 Simics model supports.
  • Range: A0 or B0
  • Default: A0. The B0 stepping features are available starting in 24.1 release, but during the project deployment, the A0 features remain being the default ones.