Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

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ID 786901
Date 8/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms 3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 E-Series HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 E-Series Universal Virtual Platform
2.1. Agilex™ 5 E-Series Universal Virtual Platform x
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview 2.1.2. Agilex™ 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. B0 Silicon Features Selection
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 E-Series HPS Components 3.1.6. Agilex™ 5 E-Series B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History

3.1.5. Additional Agilex™ 5 E-Series HPS Components

The following table lists the support status of components that do not belong to any specific subsystem. The table also shows any component limitations and the object created in the Intel® Simics® model of the Agilex™ 5 E-Series HPS.

Component Supported? Limitations | Objects
Error Checking and Correction (ECC) Controller No N/A
HPS2FPGA Bridge Yes

Limitations:

  • Supports only basic models with minimalistic features.
  • Does not support fence and drain request-based handshaking using Reset Manager.

Object:

system.board.fpga.soc_inst.hps_subsys.agilex_hps.hps2fpga
Lightweight HPS2FPGA Bridge Yes

Limitations:

  • Supports only basic models with minimalistic features.
  • Does not support fence and drain request-based handshaking using Reset Manager.

Object:

system.board.fpga.soc_inst.hps_subsys.agilex_hps.lwhps2fpga
FPGA2HPS Bridge Yes

Limitations:

  • Supports only basic models with minimalistic features.
  • Does not support fence and drain request-based handshaking using Reset Manager.

Object:

system.board.fpga.soc_inst.hps_subsys.agilex_hps.fpga2hps
FPGA2SDRAM Bridge Yes

Limitations:

  • Supports only basic models with minimalistic features.
  • Does not support fence and drain request-based handshaking using Reset Manager.

Object:

system.board.fpga.soc_inst.hps_subsys.agilex_hps.f2sdram
System Memory Management Unit (SMMU) Yes
Limitations:
  • MPFE, CCU and F2SOC TBUs are not supported.
  • Change in size of translation table mappings not supported.
  • Range-based TLB invalidation and level hint not supported.
  • Secure EL2 and Secure stage 2 translations not supported.
  • Small translation tables not supported.
  • Memory Partitioning and Monitoring not supported

Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.smmu

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