Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

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ID 786901
Date 8/08/2024
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms 3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 E-Series HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 E-Series Universal Virtual Platform
2.1. Agilex™ 5 E-Series Universal Virtual Platform x
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview 2.1.2. Agilex™ 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. B0 Silicon Features Selection
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 E-Series HPS Components 3.1.6. Agilex™ 5 E-Series B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History

4.3. Starting the Simulation

After you set up the simulation, you can start the simulation.

Start the simulation with the target script along with the simics or simics-gui applications that were created under the project directory.

The following example shows an example of how to launch the simulation by running Intel® Simics® agilex5e-universal.simics script with the simics command. 
/home/simicsUser/SimicsEnv/project-1 $ ./simics agilex5e-universal.simics

Intel Simics 6 (build 6190 linux64)© 2023 Intel Corporation
 
Use of this software is subject to appropriate license.
Type 'copyright' for details on copyright and 'help' for on-line documentation.
 
Search directories:
The current Intel Simics search path is:
   /home/simicsUser/SimicsEnv/project-1
[system.board info] Creating SD card
[system.board.nand.nand_image info] Raising read/busy pin to NAND controller
NAPT enabled with gateway 10.10.0.1/24 on link ethernet_switch0.link.
NAPT enabled with gateway fe80::2220:20ff:fe20:2000/64 on link ethernet_switch0.link.
Loading SD image /home/simicsUser/SimicsEnv/project-1/sm_images/gsrd-console-image-agilex5.wic
:
:
simics> run
running>

When you launch the simulation with the simics command, the host terminal becomes the Intel® Simics® simulator CLI. In this terminal, you can interact with the simulation with any Intel® Simics® simulation command.

To start running the simulation, use the run Intel® Simics® CLI command.

When the simulation is run, the target system serial console shows the boot log messages. The target serial console is enabled by default, but you can disable it in the script components or Python components.

A partial view of the log showing the boot flow going from the u-boot SPL to ATF to U-Boot to Linux* login prompt is as follows: 
U-Boot SPL 2022.01 (Dec 20 2022 - 09:01:15 +0000)
Reset state: Cold
MPU           640000 kHz
L4 Main       400000 kHz
L4 sys free   100000 kHz
L4 MP         200000 kHz
L4 SP         100000 kHz
SDMMC          50000 kHz
DDR: Calibration success
DDR: Warning: DRAM size from device tree (2048 MiB)
mismatch with hardware (4096 MiB).
DDR5: 2048 MiB
:
Trying to boot from MMC1
## Checking hash(es) for config board-0 ... OK
## Checking hash(es) for Image atf ... crc32+ OK
## Checking hash(es) for Image uboot ... crc32+ OK
## Checking hash(es) for Image fdt-0 ... crc32+ OK
NOTICE:  BL31: bl31_setup
NOTICE:  BL31: Enable_MMU_EL3
NOTICE:  BL31: bl31_plat_arch_setup
NOTICE:  BL31: v2.7.0(release):8abd3026e
NOTICE:  BL31: Built : 09:00:59, Jan 13 2023

U-Boot 2022.01 (Dec 20 2022 - 09:01:15 +0000)socfpga_agilex5
 
CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A55/A76)
Model: SoCFPGA Agilex5 SoCDK
DRAM:  2 GiB
:
   Uncompressing Kernel Image
   Loading Device Tree to 00000000ffaf6000, end 00000000ffafc74f ... OK
SF: Detected mt25qu02g with page size 256 Bytes, erase size 4 KiB, total 256 MiB
Enabling QSPI at Linux DTB...
QSPI clock frequency updated
RSU: Firmware or flash content not supporting RSU
 
Starting kernel ...
 
[    0.000000] start_kernel: Kernel command line: (null)
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
[    0.000000] Linux version 5.16.0-altera (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 12.2.0, GNU ld (GNU Binutils) 2.39.0.20220819) #1 SMP PREEMPT Thu Jan 19 04:36:06 UTC 2023
[    0.000000] Machine model: SoCFPGA Agilex5 SoCDK
:
[    3.655631] random: crng init done
[    6.883283] dw-apb-uart 10c02000.serial: failed to request DMA
 
Poky (Yocto Project Reference Distro) 4.1.2 dhcp0 ttyS0
 
dhcp0 login:

For additional information about running the simulation and simulation control refer to the following sections in the Intel® Simics® Simulator for Intel® FPGAs User Guide:

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