Visible to Intel only — GUID: czi1692899458328
Ixiasoft
1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History
2.1.3.1. Boot-To-Operating System Prompt
2.1.3.2. Basic Ethernet
2.1.3.3. CPU Power-On and Boot Core Selection
2.1.3.4. Reset Flow
2.1.3.5. General Purpose I/O (GPIO) Loopback
2.1.3.6. USB Disks Hot-Plug Support
2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design
2.1.3.8. FPGA-to-HPS Bridges
2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design
2.1.3.10. USB Controller Host/Device Mode Configuration
2.1.3.11. B0 Silicon Features Selection
Visible to Intel only — GUID: czi1692899458328
Ixiasoft
2.1.1.2. HPS Subsystem Component
The HPS subsystem component corresponds to the model of the module that integrates all components associated with the HPS in the Agilex™ 5 E-Series device. It includes the HPS models, SDM mailbox, and EMIF model. A brief description of the components that integrate the HPS subsystem component is provided in the following table:
Component | Description |
---|---|
HPS Component | The HPS component block is described in Agilex 5 HPS Component. |
EMIF Component | Models an instance of the External Memory Interfaces (EMIF) for HPS Intel FPGA IP. |
SDM Component | Implements a limited functionality of the Security Device Manager (SDM) allowing servicing messages sent by the HPS component. It also includes the QSPI controller that is shared between SDM and HPS. |
This component is implemented as a Python script named sm_ghrd_subsys_hps_comp.py.