Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

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ID 786901
Date 8/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms 3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 E-Series HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 E-Series Universal Virtual Platform
2.1. Agilex™ 5 E-Series Universal Virtual Platform x
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview 2.1.2. Agilex™ 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. B0 Silicon Features Selection
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 E-Series HPS Components 3.1.6. Agilex™ 5 E-Series B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History

6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware

The following table describes a list of issues that were identified when switching from the simulation model of the Agilex™ 5 E-Series device and its virtual platform to a real hardware platform, along with the symptom of the failure and the root cause. It also indicates the reason why the issues could not be caught on the Simulation model and how they can be fixed in the HPS software. The table provides additional information, such as if the issue is related to the HPS booting flow or not.

For Intel® Simics® users, the information in this table is helpful to identify the areas that may not be exercised in the model and those that will require a special attention during the HPS software development before transitioning to real hardware.

Table 28.  Troubleshooting Issues When Migrating Software
Issue observed during software bring-up in hardware Is the issue related to booting? Root Cause Why is the issue not seen in the Intel® Simics® Model? Fix in the Software
The DDR access fails when trying to boot in hardware Yes CCU and MPFE are not initialized before accessing the DDR. Intel® Simics® does not support CCU and MPFE. It supports only the register model. Configure CCU and MPFE registers correctly before accessing DDR.
Booting with SMMU enabled fails or ADMA error seen when booting up Yes SMMU is not configured correctly. For Versions 24.1 or earlier, Intel® Simics® does not support any instances of SMMU.

For Versions 24.2 and later, the model includes SMMU support.

 Implement one of the following solutions:
  • Solution 1: Disable SMMU in the software and proceed with booting.
  • Solution 2: Configure SMMU and boot it again.
The DDR and other peripherals' access fails when trying to boot in hardware Yes Firewall registers are not configured to allow secure and non-secure transactions as per the software state. Firewall is not supported. Only the register model is available in Intel® Simics® . Configure the software firewall for secure and non-secure transactions.

PSS peripherals are not functional. For example, USB and Ethernet

Yes Clock manager's main and peripheral PLLs are not configured. In Intel® Simics® , a majority of PSS peripherals are not driven by the clock and power of the target system. Timing critical peripherals (TSN, timer, and CPU) are driven with fixed clock as defined by the target system. Configure the clock and power manager registers to supply the correct clock and power to the peripherals during the initial stage of boot as per hardware architectural specification (HAS).

SDMMC device access fails.

(Applicable only if the boot source is SDMMC)

 Yes SDMMC voltage-level registers are not configured. Intel® Simics® does not model the voltage-level details. Configure SDMMC voltage-signaling register as per the HAS.
Hardware Coherency: Without flushing cache, external initiator agents (DMA and TCU) do not see the same view of memory as core. For example, DMA descriptor created is in cache and DMA encounters invalid DMA descriptor. No Cache not flushed to maintain the hardware coherency. Intel® Simics® does not model hardware cache, and for Versions 24.1 or earlier, Intel® Simics® did not support any instances of SMMU.

For Versions 24.2 and later, the model includes SMMU support.

.

Implement one of the following solutions:

  • Solution 1: Flush or invalidate cache in core as per the scenario. This method is referred as software coherency.
  • Solution 2: Currently, SMMU global bypass register overrides memory attributes to achieve hardware cache coherency. Attributes must be outer sharable and memory type must be cached to achieve hardware coherency.

Bad block management, ECC handling, and recovery mechanism feature fails. For example, NAND, DDR.

No Not available Intel® Simics® does not model bad block management, ECC handling, and recovery mechanism. The software handles the bad block and the NAND host handles the ECC handling.
USB 2.0: Unable to attach the USB 3.1 device to the USB 2.0 port No USB 3.1 device does not support high-speed descriptors. Intel® Simics® USB 3.1 device is not backward-compatible to connect to the USB 2.0 port (high-speed). Configure the USB 2.0 host.
USB 2.0: No full-speed device support No USB 1.1 device does not support full-speed descriptors. Intel® Simics® does not model USB 1.1 devices. Configure the USB 2.0 host.
Virtual to physical address translation SMMU-dependent fails. No SMMU is not configured before accessing any translation path. For Versions 24.1 or earlier, Intel® Simics® does not support any instances of SMMU.

For Versions 24.2 and later, the model includes SMMU support.

 Configure SMMU as per the HAS.
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