Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

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ID 786901
Date 8/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms 3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 E-Series HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 E-Series Universal Virtual Platform
2.1. Agilex™ 5 E-Series Universal Virtual Platform x
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview 2.1.2. Agilex™ 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. B0 Silicon Features Selection
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 E-Series HPS Components 3.1.6. Agilex™ 5 E-Series B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History

2.1.1.3. FPGA Fabric Design

The FPGA fabric design corresponds to the logic model implemented in the FPGA fabric in the Agilex™ 5 E-Series GHRD. This model includes the following components instantiated under the qsys_top component:
  • FPGA-to-HPS bridge memory spaces are created under the FPGA fabric design and are connected to the HPS and SDRAM components through the actual FPGA-to-HPS bridges in the HPS. Initiators in the FPGA logic model use these memory spaces to start read/write operations directed to the HPS or SDRAM components.
    • The FPGA to HPS memory space (fpga2hps_mem_space) is connected to HPS through the FPGA to HPS bridge (fpga2hps).
    • The FPGA to SDRAM memory space (f2sdram_mem_space) is connected to SDRAM through the FPGA to SDRAM bridge (f2sdram).
  • On-Chip memory example design with read/write capabilities connected to the hps2fpga bridge.
  • Peripheral subsystem includes the model of three parallel input/output cores for a dip switch, a push button, and LEDs. These cores are connected via the lwhps2fpga bridge.

HPS can access the On-Chip memory and the peripheral components through the HPS-to-FPGA bridges.

For the On-Chip memory example design, the base address offset mapped to the corresponding hps2fpga bridge (base_addr parameter) in this virtual platform is set to 0x00. The On-chip memory device is modeled as a DML device using the example_design.dml file and is instantiated in the fabric example design, which is implemented as a Python script named sm_fabric_example_design_comp.py.

The peripheral subsystem is mapped under the lwhps2fpga bridge at a 0x20000000 address. The peripheral subsystem is implemented as a Python script in the sm_ghrd_subsys_periph_comp.py file. Here, the IP components are instantiated and mapped at their memory region (relative to the mapping address indicated above). The DIP switch and push button can trigger an interrupt to the HPS on the assertion of the corresponding input signal. The following table describes the interrupts defined and their connections with the HPS under the qsys_top component:

Table 5.  Defined Interrupts and Their Connections
Component Interrupt HPS Interrupt Connection
button_pio periph_button_irq f2s_fpga_irq[0] – SIP 49
dipsw_pio periph_dipsw_irq f2s_fpga_irq[1] – SIP 50

The following diagram shows the peripheral subsystem interrupts connection:

Figure 2. Peripheral Subsystem Interrupts Connection
Note: In the current implementation of this virtual platform, all bridges (FPGA/HPS in both directions) are released from reset at POR by the SDM mailbox model. However, in the real hardware, the HPS software performs this task.

A block diagram of the FPGA Fabric design is shown in the following figure:

Figure 3. FPGA Fabric Design Block Diagram

The hierarchical names of the FPGA Fabric design components are:

  • FPGA On-Chip memory example design connected to hps2fpga bridge: system.board.fpga.soc_inst.example_design
  • Peripheral subsystem components connected to lwhps2fpga bridge:
    • system.board.fpga.soc_inst.periph_subsys
    • system.board.fpga.soc_inst.periph_subsys.button_pio
    • system.board.fpga.soc_inst.periph_subsys.dipsw_pio
    • system.board.fpga.soc_inst.periph_subsys.led_pio
  • FPGA-to-HPS bridge memory space for HPS (fpga2hps_mem_space): system.board.fpga.soc_inst.fpga2hps_mem_space
  • FPGA-to-HPS bridge memory space for SDRAM (f2sdram_mem_space): system.board.fpga.soc_inst.f2sdram_mem_space
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