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1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History
2.1.3.1. Boot-To-Operating System Prompt
2.1.3.2. Basic Ethernet
2.1.3.3. CPU Power-On and Boot Core Selection
2.1.3.4. Reset Flow
2.1.3.5. General Purpose I/O (GPIO) Loopback
2.1.3.6. USB Disks Hot-Plug Support
2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design
2.1.3.8. FPGA-to-HPS Bridges
2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design
2.1.3.10. USB Controller Host/Device Mode Configuration
2.1.3.11. B0 Silicon Features Selection
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3.5. Modeling Support Limitations
The following diagram shows a graphical representation of the modeling support of each of the components that integrate the Agilex™ 5 E-Series Universal Virtual Platform Intel® Simics® model.
Figure 10. Agilex™ 5 E-Series Universal Virtual Platform Intel® Simics® Model Limitation Block DiagramThe colors in the diagram (see legend) signify the components based on the level of modeling support:
- Minimal feature: Supports very limited functionality that allow you to exercise very basic functionality.
- Supported: Main features of the component being modeled.
- Not supported: The model does not support any real functional feature related to the component.
For specific limitations in each component, refer to sections corresponding to each component in this chapter (Agilex 5 E-Series Virtual Platform Component Intel Simics Models).