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1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History
2.1.3.1. Boot-To-Operating System Prompt
2.1.3.2. Basic Ethernet
2.1.3.3. CPU Power-On and Boot Core Selection
2.1.3.4. Reset Flow
2.1.3.5. General Purpose I/O (GPIO) Loopback
2.1.3.6. USB Disks Hot-Plug Support
2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design
2.1.3.8. FPGA-to-HPS Bridges
2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design
2.1.3.10. USB Controller Host/Device Mode Configuration
2.1.3.11. B0 Silicon Features Selection
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2.1.3.3. CPU Power-On and Boot Core Selection
The virtual platform supports the configuration of the CPU power-on settings and the CPU boot core selection.
This configuration is defined at the target script level with the following parameters:
- hps_boot_core
- hps_core0_1_power_on
- hps_core2_power_on
- hps_core3_power_on
These parameters correspond to the similar parameters set in the Hard Processor System Agilex™ 5 FPGA IP.
Based on the CPU power and boot configuration, the virtual platform exposes only the appropriate number of cores available to the target software. The virtual platform supports symmetric multiprocessing (SMP) when multiple CPUs are enabled.