Nios® V Processor Software Developer Handbook

ID 743810
Date 7/08/2024
Public
Document Table of Contents

10. Cache and Tightly-Coupled Memory

Nios® V/g processor core supports tightly-coupled memory, instruction, and data caches. This chapter discusses cache-related issues that you need to consider to ensure the program executes correctly on the Nios® V processor. Most software based on the Nios® V processor hardware abstraction layer (HAL) works correctly without special accommodations for caches. However, some software must manage the cache directly.

For code that needs direct control over the cache, the Nios® V processor architecture provides facilities to perform the following actions:
  • Initialize lines in the instruction and data caches.
  • Flush lines in the instruction and data caches.
  • Bypass the data cache using peripheral regions.