Nios® V Processor Software Developer Handbook

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ID 743810
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. Overview of Nios® V Embedded Processor Development 2. Getting Started with the Graphical User Interface 3. Getting Started from the Command Line 4. Nios® V Processor Software Development and Implementation 5. Nios® V Processor Board Support Package Editor 6. Overview of the Hardware Abstraction Layer 7. Developing Programs Using the Hardware Abstraction Layer 8. Developing Device Drivers for the Hardware Abstraction Layer 9. Exception Handling 10. Cache and Tightly-Coupled Memory 11. MicroC/OS-II Real-Time Operating System 12. MicroC/TCP-IP Protocol Stack 13. FreeRTOS* Real-Time Operating System 14. Read-Only Zip File System 15. Publishing Component Information to Embedded Software 16. Nios® V Processor Appendix A. Nios® V Processor Software Developer Handbook Archives 17. Revision History for the Nios® V Processor Software Developer Handbook
1. Overview of Nios® V Embedded Processor Development x
1.1. Nios® V Processor Software Development Environment 1.2. Nios® V Processor Software Project Types 1.3. Nios® V Processor Development Tools 1.4. Nios® V Processor Software Programs
1.1. Nios® V Processor Software Development Environment x
1.1.1. Quartus® Prime Software Support
1.3. Nios® V Processor Development Tools x
1.3.1. Nios® V Processor Command Line Utilities Tools 1.3.2. Board Support Package Editor 1.3.3. Ashling* RiscFree* IDE for Intel® FPGAs
1.4. Nios® V Processor Software Programs x
1.4.1. CMakeLists.txt and Nios® V Processor Tools
2. Getting Started with the Graphical User Interface x
2.1. Using Ashling* RiscFree* IDE for Intel® FPGAs 2.2. Using BSP Editor 2.3. Using Quartus Programmer
3. Getting Started from the Command Line x
3.1. Advantages of Command Line Software Development 3.2. Outline of the Nios® V Processor Tools Command Line
3.2. Outline of the Nios® V Processor Tools Command Line x
3.2.1. Command Line Utilities
3.2.1. Command Line Utilities x
3.2.1.1. niosv-bsp 3.2.1.2. niosv-app 3.2.1.3. niosv-download
4. Nios® V Processor Software Development and Implementation x
4.1. Nios® V Processor Tools 4.2. Nios® V Processor Software File Tree 4.3. Nios® V Processor Software Development Flow 4.4. Developing with the Hardware Abstraction Layer
4.1. Nios® V Processor Tools x
4.1.1. Nios® V Processor Tools Overview 4.1.2. Nios® V Processor Software Build Tools
4.1.2. Nios® V Processor Software Build Tools x
4.1.2.1. Nios® V Processor Software Build Tools Graphical User Interface 4.1.2.2. Nios® V Processor Software Build Tools Command Line Interface 4.1.2.3. What the Build Tools Create
4.1.2.1. Nios® V Processor Software Build Tools Graphical User Interface x
4.1.2.1.1. BSP Editor 4.1.2.1.2. Ashling* RiscFree* IDE for Intel FPGAs 4.1.2.1.3. Nios V Command Shell
4.1.2.2. Nios® V Processor Software Build Tools Command Line Interface x
4.1.2.2.1. Nios® V Processor Command Line Utilities 4.1.2.2.2. File Format Conversion Tools 4.1.2.2.3. Other Utilities Tools
4.1.2.3. What the Build Tools Create x
4.1.2.3.1. Applications and Libraries 4.1.2.3.2. Board Support Packages 4.1.2.3.3. CMakeLists.txt
4.2. Nios® V Processor Software File Tree x
4.2.1. Building Single Application and Single BSP 4.2.2. Building Single Application, Single Library, and BSP 4.2.3. Building Multiple Applications and Single BSP 4.2.4. Building BSP Library
4.2.1. Building Single Application and Single BSP x
4.2.1.1. Build Commands 4.2.1.2. File Tree Directory
4.2.2. Building Single Application, Single Library, and BSP x
4.2.2.1. Build Commands 4.2.2.2. File Tree Directory
4.2.3. Building Multiple Applications and Single BSP x
4.2.3.1. Build Commands 4.2.3.2. File Tree Directory
4.2.4. Building BSP Library x
4.2.4.1. Build Commands 4.2.4.2. File Tree Directory
4.3. Nios® V Processor Software Development Flow x
4.3.1. Getting Started 4.3.2. Configuring BSP Projects 4.3.3. Configuring the Application Project 4.3.4. Building and Running Nios® V Processor Software
4.3.2. Configuring BSP Projects x
4.3.2.1. Selecting the Operating System 4.3.2.2. Intel HAL Configuration Tips 4.3.2.3. Micrium MicroC/OS-II Configuration tips 4.3.2.4. Configuring FreeRTOS* 4.3.2.5. Adding Software Package 4.3.2.6. Using Tcl Script with BSP Editor 4.3.2.7. Exporting Tcl Scripts with BSP Editor 4.3.2.8. Importing Tcl Script to Create a New BSP
4.3.3. Configuring the Application Project x
4.3.3.1. Application Configuration Tips 4.3.3.2. Linking User Libraries
4.3.4. Building and Running Nios® V Processor Software x
4.3.4.1. Building the Nios® V Processor Software 4.3.4.2. Downloading and Running the Nios® V Processor Software 4.3.4.3. Nios® V Processor Software Debugging 4.3.4.4. Run Time Stack Checking 4.3.4.5. Ensuring Software Project Coherency
4.3.4.2. Downloading and Running the Nios® V Processor Software x
4.3.4.2.1. Communicating with the Target Device
4.3.4.5. Ensuring Software Project Coherency x
4.3.4.5.1. Recommended Development Practice 4.3.4.5.2. Recommended Architecture Practice
4.4. Developing with the Hardware Abstraction Layer x
4.4.1. Hardware Abstraction Layer Services 4.4.2. System Startup in HAL-based Application 4.4.3. HAL Peripheral Services 4.4.4. Handling Exceptions
4.4.1. Hardware Abstraction Layer Services x
4.4.1.1. HAL Configuration Options 4.4.1.2. Configuring the Boot Environment
4.4.2. System Startup in HAL-based Application x
4.4.2.1. System Initialization 4.4.2.2. crt0 Initialization 4.4.2.3. HAL Initialization
4.4.3. HAL Peripheral Services x
4.4.3.1. Timer Devices 4.4.3.2. Character Mode Devices 4.4.3.3. Flash Memory Devices
4.4.3.1. Timer Devices x
4.4.3.1.1. System Clock Timer 4.4.3.1.2. Timestamp Timer
4.4.3.2. Character Mode Devices x
4.4.3.2.1. stdin, stdout and stderr 4.4.3.2.2. Blocking versus Non-Blocking I/O 4.4.3.2.3. Adding Your Own Character Mode Device
4.4.3.3. Flash Memory Devices x
4.4.3.3.1. Memory Initialization, Querying, and Device Support 4.4.3.3.2. Accessing Flash Memory 4.4.3.3.3. Configuration and Use Limitations 4.4.3.3.4. Direct Memory Access Devices 4.4.3.3.5. Unsupported Devices
4.4.4. Handling Exceptions x
4.4.4.1. Modifying the Exception Handler
5. Nios® V Processor Board Support Package Editor x
5.1. Board Support Packages 5.2. Common BSP Tasks 5.3. Details of BSP Creation 5.4. Tcl Scripts for BSP Settings 5.5. Revising Your BSP 5.6. Specifying BSP Defaults 5.7. Device Drivers and Software Packages 5.8. Boot Configurations for Intel FPGA Embedded Software
5.1. Board Support Packages x
5.1.1. Overview of BSP Creation 5.1.2. Nios® V Processor BSP Components
5.1.2. Nios® V Processor BSP Components x
5.1.2.1. Hardware Abstraction Layer 5.1.2.2. newlib C Standard Library 5.1.2.3. Device Drivers 5.1.2.4. Optional Software Packages 5.1.2.5. Optional Real-Time Operating System
5.2. Common BSP Tasks x
5.2.1. Creating a BSP for an Intel® FPGA Development Board 5.2.2. Adding the BSP Editor to Tool Flow 5.2.3. Linking and Locating 5.2.4. Other BSP Tasks
5.2.2. Adding the BSP Editor to Tool Flow x
5.2.2.1. Using Version Control 5.2.2.2. Copying, Moving, or Renaming a BSP 5.2.2.3. Passing the BSP to Another Developer
5.2.2.1. Using Version Control x
5.2.2.1.1. Creating BSP by Running User-defined Script to Call niosv-bsp 5.2.2.1.2. Creating Script that Uses the Command Line Tools
5.2.3. Linking and Locating x
5.2.3.1. Creating Memory Initialization Files 5.2.3.2. Modifying Linker Memory Regions 5.2.3.3. Creating a Custom Linker Section 5.2.3.4. Changing the Linker Section Mapping
5.2.3.3. Creating a Custom Linker Section x
5.2.3.3.1. Creating a Linker Section for an Existing Region 5.2.3.3.2. Dividing a Linker Region to Create a New Region and Section
5.2.4. Other BSP Tasks x
5.2.4.1. Querying Settings 5.2.4.2. Managing Device Drivers 5.2.4.3. Controlling the stdio Device 5.2.4.4. Configuring Optimization and Debugger Options 5.2.4.5. Configuring RISC-V Compiler
5.3. Details of BSP Creation x
5.3.1. BSP Settings File Creation 5.3.2. BSP Files and Folders 5.3.3. Linker Map Validation 5.3.4. Hierarchical Platform Designer Systems
5.3.2. BSP Files and Folders x
5.3.2.1. Generated and Copied Files 5.3.2.2. BSP Files
5.3.4. Hierarchical Platform Designer Systems x
5.3.4.1. Handling Hierarchical Systems
5.4. Tcl Scripts for BSP Settings x
5.4.1. Calling a Custom BSP Tcl Script
5.4.1. Calling a Custom BSP Tcl Script x
5.4.1.1. Tcl Script to Examine Hardware and Choose Settings
5.5. Revising Your BSP x
5.5.1. Regenerating Your BSP 5.5.2. Updating Your BSP 5.5.3. Recreating Your BSP
5.5.1. Regenerating Your BSP x
5.5.1.1. What Happens 5.5.1.2. When to Regenerate Your BSP
5.5.2. Updating Your BSP x
5.5.2.1. What Happens 5.5.2.2. When to Update Your BSP
5.5.3. Recreating Your BSP x
5.5.3.1. What Happens 5.5.3.2. When to Recreate Your BSP
5.6. Specifying BSP Defaults x
5.6.1. Top Level Tcl Script for BSP Defaults
5.6.1. Top Level Tcl Script for BSP Defaults x
5.6.1.1. Specifying the Default stdio Device 5.6.1.2. Specifying the Default System Timer 5.6.1.3. Specifying the Default Memory Map 5.6.1.4. Specifying the Default Bootloader Parameters 5.6.1.5. Specifying the Default Exception Parameter
5.8. Boot Configurations for Intel FPGA Embedded Software x
5.8.1. Memory Types 5.8.2. Boot from Flash Configuration 5.8.3. Run from Initialized Memory Configuration 5.8.4. Run-time Configurable Reset Configuration
6. Overview of the Hardware Abstraction Layer x
6.1. Getting Started with the Hardware Abstraction Layer 6.2. HAL Architecture for Embedded Software Systems 6.3. Embedded Hardware Supported by the HAL
6.2. HAL Architecture for Embedded Software Systems x
6.2.1. Services 6.2.2. Applications versus Drivers 6.2.3. Generic Device Models 6.2.4. C Standard Library—Newlib, Picolibc
6.2.3. Generic Device Models x
6.2.3.1. Device Model Classes 6.2.3.2. Benefits to Application Developers 6.2.3.3. Benefits to Device Driver Developers
6.3. Embedded Hardware Supported by the HAL x
6.3.1. Nios® V Processor Core Support 6.3.2. Supported Peripherals
6.3.2. Supported Peripherals x
6.3.2.1. Full HAL Support 6.3.2.2. Partial HAL Support
7. Developing Programs Using the Hardware Abstraction Layer x
7.1. HAL BSP Settings 7.2. The Nios® V Processor Embedded Project Structure 7.3. The system.h System Description File 7.4. Data Widths and the HAL Type Definitions 7.5. UNIX-Style Interface 7.6. Using Character-Mode Devices 7.7. Using Timer Devices 7.8. Using Flash Devices 7.9. Using DMA Devices 7.10. Interrupt Controllers 7.11. Reducing Code Footprint in Embedded Systems 7.12. Boot Sequence and Entry Point 7.13. Memory Usage 7.14. Working with HAL Source Files
7.6. Using Character-Mode Devices x
7.6.1. Standard Input, Standard Output and Standard Error 7.6.2. General Access to Character Mode Devices 7.6.3. C++ Streams 7.6.4. /dev/null 7.6.5. Lightweight Character-Mode I/O 7.6.6. Intel FPGA Logging Functions
7.6.6. Intel FPGA Logging Functions x
7.6.6.1. Enabling Logging 7.6.6.2. Extra Logging Options 7.6.6.3. Logging Levels 7.6.6.4. Example: Creating a BSP with Logging 7.6.6.5. Custom Logging Messages 7.6.6.6. Intel FPGA Logging Files
7.7. Using Timer Devices x
7.7.1. System Clock Driver 7.7.2. Alarms 7.7.3. Timestamp Driver
7.8. Using Flash Devices x
7.8.1. Simple Flash Access 7.8.2. Block Erasure or Corruption 7.8.3. Fine-Grained Flash Access
7.8.3. Fine-Grained Flash Access x
7.8.3.1. alt_get_flash_info() 7.8.3.2. alt_erase_flash() 7.8.3.3. alt_write_flash_block()
7.9. Using DMA Devices x
7.9.1. DMA Transmit Channels 7.9.2. DMA Receive Channels
7.9.2. DMA Receive Channels x
7.9.2.1. Memory-to-Memory DMA Transactions
7.11. Reducing Code Footprint in Embedded Systems x
7.11.1. Apply Compiler Flags 7.11.2. Use Small Variant Device Drivers 7.11.3. Reduce the File Descriptor Pool 7.11.4. Use /dev/null 7.11.5. Use a Smaller File I/O Library 7.11.6. Use the Minimal Character-Mode API 7.11.7. Eliminate Unused Device Drivers 7.11.8. Use the Picolibc Library 7.11.9. Eliminate Unused alt_load() 7.11.10. Eliminate Unneeded Exit Code
7.11.1. Apply Compiler Flags x
7.11.1.1. Apply Different Compiler Flags in BSP and APP 7.11.1.2. Apply Different Compiler Flags within a Source File
7.11.5. Use a Smaller File I/O Library x
7.11.5.1. Definition of 'asnprintf()' 7.11.5.2. Use UNIX-Style File I/O 7.11.5.3. Emulate ANSI C Functions
7.11.10. Eliminate Unneeded Exit Code x
7.11.10.1. Eliminate Clean Exit 7.11.10.2. Eliminate All Exit Code 7.11.10.3. Turn off C++ Support
7.12. Boot Sequence and Entry Point x
7.12.1. Hosted Versus Free-Standing Applications 7.12.2. Boot Sequence for HAL-Based Programs 7.12.3. Customizing the Boot Sequence
7.12.2. Boot Sequence for HAL-Based Programs x
7.12.2.1. System Initialization Code Boot Sequence 7.12.2.2. Default Implementation Steps
7.13. Memory Usage x
7.13.1. Memory Sections 7.13.2. Assigning Code and Data to Memory Partitions 7.13.3. Placement of the Heap and Stack 7.13.4. Global Pointer Register 7.13.5. Boot Modes
7.13.2. Assigning Code and Data to Memory Partitions x
7.13.2.1. Simple Placement Options 7.13.2.2. Advanced Placement Options
7.14. Working with HAL Source Files x
7.14.1. Finding HAL Files 7.14.2. Overriding HAL Functions
8. Developing Device Drivers for the Hardware Abstraction Layer x
8.1. Driver Integration in the HAL API 8.2. The HAL Peripheral-Specific API 8.3. Preparing for HAL Driver Development 8.4. Development Flow for Creating Device Drivers 8.5. Nios® V Processor Hardware Design Concepts 8.6. Accessing Hardware 8.7. Creating Embedded Drivers for HAL Device Classes 8.8. Integrating a Device Driver in the HAL 8.9. Creating a Custom Device Driver for the HAL 8.10. Reducing Code Footprint in HAL Embedded Drivers 8.11. HAL Namespace Allocation 8.12. Overriding the HAL Default Device Drivers
8.5. Nios® V Processor Hardware Design Concepts x
8.5.1. The Relationship Between the .qsys File and system.h 8.5.2. Using the System Generation Tool to Optimize Hardware 8.5.3. Components, Devices, and Peripherals
8.7. Creating Embedded Drivers for HAL Device Classes x
8.7.1. Character-Mode Device Drivers 8.7.2. File Subsystem Drivers 8.7.3. Timer Device Drivers 8.7.4. Flash Device Drivers 8.7.5. DMA Device Drivers
8.7.1. Character-Mode Device Drivers x
8.7.1.1. Create a Device Instance 8.7.1.2. Register a Character Device
8.7.1.1. Create a Device Instance x
8.7.1.1.1. Modifying the Global Error Status, errno 8.7.1.1.2. Default Behavior for Functions Defined in alt_dev
8.7.2. File Subsystem Drivers x
8.7.2.1. Create a Device Instance 8.7.2.2. Register a File Subsystem Device
8.7.3. Timer Device Drivers x
8.7.3.1. System Clock Driver 8.7.3.2. Timestamp Driver
8.7.4. Flash Device Drivers x
8.7.4.1. Create a Flash Driver 8.7.4.2. Register a Flash Device
8.7.5. DMA Device Drivers x
8.7.5.1. DMA Transmit Channel 8.7.5.2. DMA Receive Channel
8.8. Integrating a Device Driver in the HAL x
8.8.1. Overview 8.8.2. Assumptions and Requirements 8.8.3. Nios® V Processor BSP Generation Flow 8.8.4. File Names and Locations 8.8.5. Driver and Software Package Tcl Script Creation
8.8.3. Nios® V Processor BSP Generation Flow x
8.8.3.1. Component Discovery 8.8.3.2. Device Driver Versions 8.8.3.3. Device Driver and Software Package Inclusion
8.8.3.3. Device Driver and Software Package Inclusion x
8.8.3.3.1. Specific Requests 8.8.3.3.2. No Specific Requests
8.8.4. File Names and Locations x
8.8.4.1. Source Code Discovery
8.8.5. Driver and Software Package Tcl Script Creation x
8.8.5.1. Example Device Driver File Hierarchy and Naming 8.8.5.2. Tcl Command Walkthrough for a Typical Driver or Software Package 8.8.5.3. Creating Settings for Device Drivers and Software Packages
8.8.5.2. Tcl Command Walkthrough for a Typical Driver or Software Package x
8.8.5.2.1. Creating and Naming the Driver or Package 8.8.5.2.2. Identifying the Hardware Component Class 8.8.5.2.3. Setting the BSP Type 8.8.5.2.4. Specifying an Operating System 8.8.5.2.5. Specifying Source Files 8.8.5.2.6. Specifying a Subdirectory 8.8.5.2.7. Enabling Software Initialization 8.8.5.2.8. Adding Include Paths 8.8.5.2.9. Version Compatibility
8.8.5.3. Creating Settings for Device Drivers and Software Packages x
8.8.5.3.1. How Settings Affect the Generated BSP 8.8.5.3.2. Data Types 8.8.5.3.3. Setting Destination Files 8.8.5.3.4. Setting Display Name 8.8.5.3.5. Setting Identifier 8.8.5.3.6. Setting Default Value 8.8.5.3.7. Setting Description 8.8.5.3.8. Setting Creation Example
8.9. Creating a Custom Device Driver for the HAL x
8.9.1. Header Files and alt_sys_init.c 8.9.2. Device Driver Source Code
8.9.1. Header Files and alt_sys_init.c x
8.9.1.1. Creating alt_sys_init.c Based on Associated Header Files
8.9.2. Device Driver Source Code x
8.9.2.1. altera_avalon_jtag_uart.h Defining Macros
9. Exception Handling x
9.1. Nios® V Processor Exception Handling Overview 9.2. Nios® V Processor Hardware Interrupt Service Routines 9.3. Nios® V Processor Software Interrupt Service Routines 9.4. Nios® V Processor Timer Interrupt Service Routine 9.5. Improving Nios® V Processor ISR Performance 9.6. Debugging Nios® V Processor ISRs 9.7. HAL Exception Handling System Implementation 9.8. Nios® V Processor Instruction-Related Exception Handler
9.1. Nios® V Processor Exception Handling Overview x
9.1.1. Exception Handling Terminology 9.1.2. Hardware Interrupt Controllers 9.1.3. How the Hardware works 9.1.4. Latency and Response Time
9.1.2. Hardware Interrupt Controllers x
9.1.2.1. Internal Interrupt Concepts
9.1.3. How the Hardware works x
9.1.3.1. How the Internal Interrupt Controller Works
9.1.4. Latency and Response Time x
9.1.4.1. Internal Interrupt Controller
9.2. Nios® V Processor Hardware Interrupt Service Routines x
9.2.1. HAL APIs for Hardware Interrupts 9.2.2. Writing a Hardware ISR 9.2.3. Registering a Hardware ISR 9.2.4. Enabling and Disabling Interrupts 9.2.5. C Example
9.2.1. HAL APIs for Hardware Interrupts x
9.2.1.1. Enhanced HAL Hardware Interrupt API
9.2.2. Writing a Hardware ISR x
9.2.2.1. Using General Exception Funnels 9.2.2.2. Running in a Restricted Environment
9.2.3. Registering a Hardware ISR x
9.2.3.1. Methods the HAL Uses to Register the ISR
9.2.5. C Example x
9.2.5.1. Writing a Hardware ISR to Service a Button PIO Interrupt 9.2.5.2. Registering the Button PIO ISR with the HAL
9.3. Nios® V Processor Software Interrupt Service Routines x
9.3.1. HAL APIs for Software Interrupt 9.3.2. Writing a Software ISR 9.3.3. Registering a Software ISR 9.3.4. Enabling and Disabling Interrupts 9.3.5. C Example
9.3.5. C Example x
9.3.5.1. Writing a Software ISR 9.3.5.2. Registering the Software ISR with the HAL
9.5. Improving Nios® V Processor ISR Performance x
9.5.1. Software Performance Improvements 9.5.2. Hardware Performance Improvements
9.5.1. Software Performance Improvements x
9.5.1.1. Execute Time-Intensive Algorithms in the Application Context 9.5.1.2. Implement Time-Intensive Algorithms in Hardware 9.5.1.3. Increase Buffer Size 9.5.1.4. Use Double Buffering 9.5.1.5. Keep Interrupts Enabled 9.5.1.6. Use Fast Memory 9.5.1.7. Use a Separate Exception Stack 9.5.1.8. Use Nested Hardware Interrupts 9.5.1.9. Use Compiler Optimization
9.5.1.7. Use a Separate Exception Stack x
9.5.1.7.1. Separate General Exception Stack
9.5.2. Hardware Performance Improvements x
9.5.2.1. Add Fast Memory 9.5.2.2. Add a DMA Controller 9.5.2.3. Place the Handler in Fast Memory 9.5.2.4. Select Hardware Interrupt Priorities
9.5.2.4. Select Hardware Interrupt Priorities x
9.5.2.4.1. Hardware Interrupt Priorities with the Internal Interrupt Controller
9.7. HAL Exception Handling System Implementation x
9.7.1. Exception Handling System Structure 9.7.2. General Exception Funnels 9.7.3. Hardware Interrupt Funnel 9.7.4. Software Exception Funnel 9.7.5. Software Interrupt Handler 9.7.6. Timer Interrupt Handler
9.7.2. General Exception Funnels x
9.7.2.1. Exception Occurs 9.7.2.2. Exception Dispatch with the Internal Interrupt Controller 9.7.2.3. Returning from Exceptions
9.7.3. Hardware Interrupt Funnel x
9.7.3.1. Hardware Interrupt Funnel for the Internal Interrupt Controller
9.7.4. Software Exception Funnel x
9.7.4.1. Instruction-Related Exceptions 9.7.4.2. Miscellaneous Exceptions 9.7.4.3. Invalid Instructions
9.8. Nios® V Processor Instruction-Related Exception Handler x
9.8.1. Writing an Instruction-Related Exception Handler 9.8.2. Registering an Instruction-Related Exception Handler 9.8.3. Removing an Instruction-Related Exception Handler 9.8.4. Debugging for Instruction-Related Exception Handler
9.8.1. Writing an Instruction-Related Exception Handler x
9.8.1.1. Exception Cause Codes
9.8.4. Debugging for Instruction-Related Exception Handler x
9.8.4.1. Enable JTAG UART polling operation 9.8.4.2. Example of Instruction-Related Exception Handler 9.8.4.3. Adding Custom Exception Handler
10. Cache and Tightly-Coupled Memory x
10.1. Nios® V Processor Cache Implementation 10.2. Initializing Cache after Reset 10.3. Device Driver Cache Considerations 10.4. Managing Cache in Multi-Master and Multi-Processor Systems 10.5. Tightly-Coupled Memory
11. MicroC/OS-II Real-Time Operating System x
11.1. Overview of the MicroC/OS-II RTOS 11.2. Other RTOS Providers 11.3. The Nios® V Processor Implementation of MicroC/OS-II 11.4. Implementing MicroC/OS-II Projects for the Nios® V Processor
11.1. Overview of the MicroC/OS-II RTOS x
11.1.1. Support and Licensing
11.3. The Nios® V Processor Implementation of MicroC/OS-II x
11.3.1. MicroC/OS-II Architecture 11.3.2. MicroC/OS-II Device Drivers 11.3.3. Thread-Safe Drivers 11.3.4. The newlib ANSI C Standard Library 11.3.5. Interrupt Service Routines for MicroC/OS-II
12. MicroC/TCP-IP Protocol Stack x
12.1. Overview of the MicroC/TCP-IP Protocol Stack 12.2. Support and Licensing 12.3. Prerequisites for Understanding the MicroC/TCP-IP Protocol Stack 12.4. Introduction to the MicroC/TCP-IP Protocol Stack - Nios® V Processor Edition 12.5. The MicroC/TCP-IP Protocol Stack Files and Directories 12.6. Enabling MicroC/TCP-IP Protocol Stack 12.7. Using the MicroC/TCP-IP Protocol Stack
12.4. Introduction to the MicroC/TCP-IP Protocol Stack - Nios® V Processor Edition x
12.4.1. Nios® V Processor System Requirements
12.7. Using the MicroC/TCP-IP Protocol Stack x
12.7.1. Initializing the Stack 12.7.2. Network IP configuration 12.7.3. Example applications
12.7.3. Example applications x
12.7.3.1. simple_socket_server.c 12.7.3.2. app_iperf.c
13. FreeRTOS* Real-Time Operating System x
13.1. Overview of the FreeRTOS* 13.2. The Nios® V Processor Implementation of FreeRTOS* 13.3. Implementing FreeRTOS™ Project for the Nios® V Processor
13.1. Overview of the FreeRTOS* x
13.1.1. Support and Licensing
13.2. The Nios® V Processor Implementation of FreeRTOS* x
13.2.1. FreeRTOS* Architecture 13.2.2. FreeRTOS* Device Drivers 13.2.3. Thread-Safe HAL Drivers 13.2.4. The newlib ANSI C Standard Library
13.3. Implementing FreeRTOS™ Project for the Nios® V Processor x
13.3.1. Create FreeRTOS BSP Project 13.3.2. Configure FreeRTOS Features 13.3.3. Write FreeRTOS-based Source Codes 13.3.4. Generate Application CMake File 13.3.5. Build FreeRTOS BSP and Application Projects
14. Read-Only Zip File System x
14.1. Read-Only Zip File System in BSP Editor 14.2. Preparing the Zip File 14.3. Programming the Zip File to Flash 14.4. Programming the Zip File to On-Chip ROM
14.3. Programming the Zip File to Flash x
14.3.1. General Purpose QSPI Flash 14.3.2. Active Serial Configuration Flash in Control-block Based Devices 14.3.3. Active Serial Configuration Flash in SDM Based Devices
15. Publishing Component Information to Embedded Software x
15.1. Embedded Component Information Flow 15.2. Embedded Software Assignments
15.2. Embedded Software Assignments x
15.2.1. C Macro Namespace 15.2.2. Configuration Namespace
15.2.1. C Macro Namespace x
15.2.1.1. Generated Macro in system.h 15.2.1.2. GCC C/C++ 32-bit Processor Constants
15.2.2. Configuration Namespace x
15.2.2.1. Configuration Data Types 15.2.2.2. Component Configuration Information 15.2.2.3. Memory-Mapped Slave Information
16. Nios® V Processor Appendix x
16.1. HAL API 16.2. Nios® V Processor Tools Reference 16.3. GNU RISC-V Embedded GCC Toolchain Reference 16.4. Settings Managed by Nios® V Processor Board Support Package Editor 16.5. Board Support Package Tcl Commands 16.6. Nios® V Processor Design Example 16.7. Manual System PATH Variable Setup
16.1. HAL API x
16.1.1. HAL API Reference 16.1.2. HAL Standard Types
16.1.1. HAL API Reference x
16.1.1.1. _exit() 16.1.1.2. _rename() 16.1.1.3. alt_dcache_flush() 16.1.1.4. alt_dcache_flush_all() 16.1.1.5. alt_icache_flush_all() 16.1.1.6. alt_dcache_flush_no_writeback() 16.1.1.7. alt_icache_flush_all() 16.1.1.8. alt_icache_flush() 16.1.1.9. alt_alarm_start() 16.1.1.10. alt_alarm_stop() 16.1.1.11. alt_dma_rxchan_depth() 16.1.1.12. alt_dma_rxchan_close() 16.1.1.13. alt_dev_reg() 16.1.1.14. alt_dma_rxchan_open() 16.1.1.15. alt_dma_rxchan_prepare() 16.1.1.16. alt_dma_rxchan_reg() 16.1.1.17. alt_dma_txchan_close() 16.1.1.18. alt_dma_txchan_ioctl() 16.1.1.19. alt_dma_txchan_open() 16.1.1.20. alt_dma_txchan_reg() 16.1.1.21. alt_flash_close_dev() 16.1.1.22. alt_exception_cause_generated_bad_addr() 16.1.1.23. alt_erase_flash_block() 16.1.1.24. alt_dma_rxchan_ioctl() 16.1.1.25. alt_dma_txchan_space() 16.1.1.26. alt_dma_txchan_send() 16.1.1.27. alt_flash_open_dev() 16.1.1.28. alt_fs_reg() 16.1.1.29. alt_get_flash_info() 16.1.1.30. alt_ic_irq_disable() 16.1.1.31. alt_ic_irq_enabled() 16.1.1.32. alt_ic_isr_register() 16.1.1.33. alt_ic_irq_enable() 16.1.1.34. alt_instruction_exception_register() 16.1.1.35. alt_irq_cpu_enable_interrupts () 16.1.1.36. alt_irq_disable_all() 16.1.1.37. alt_irq_enable_all() 16.1.1.38. alt_irq_enabled() 16.1.1.39. alt_irq_init() 16.1.1.40. alt_irq_pending () 16.1.1.41. alt_llist_insert() 16.1.1.42. alt_llist_remove() 16.1.1.43. alt_load_section() 16.1.1.44. alt_nticks() 16.1.1.45. alt_read_flash() 16.1.1.46. alt_tick() 16.1.1.47. alt_ticks_per_second() 16.1.1.48. alt_timestamp() 16.1.1.49. alt_timestamp_freq() 16.1.1.50. alt_timestamp_start() 16.1.1.51. alt_write_flash() 16.1.1.52. alt_write_flash_block() 16.1.1.53. close() 16.1.1.54. fstat() 16.1.1.55. fork() 16.1.1.56. fcntl() 16.1.1.57. execve() 16.1.1.58. getpid() 16.1.1.59. kill() 16.1.1.60. stat() 16.1.1.61. settimeofday() 16.1.1.62. wait() 16.1.1.63. unlink() 16.1.1.64. sbrk() 16.1.1.65. link() 16.1.1.66. lseek() 16.1.1.67. open() 16.1.1.68. alt_sysclk_init() 16.1.1.69. times() 16.1.1.70. read() 16.1.1.71. write() 16.1.1.72. usleep() 16.1.1.73. alt_lock_flash() 16.1.1.74. gettimeofday() 16.1.1.75. ioctl() 16.1.1.76. isatty() 16.1.1.77. alt_niosv_enable_msw_interrupt() 16.1.1.78. alt_niosv_disable_msw_interrupt() 16.1.1.79. alt_niosv_is_msw_interrupt_enabled() 16.1.1.80. alt_niosv_trigger_msw_interrupt() 16.1.1.81. alt_niosv_clear_msw_interrupt() 16.1.1.82. alt_niosv_register_msw_interrupt_handler()
16.1.2. HAL Standard Types x
16.1.2.1. alt_getchar() 16.1.2.2. alt_putstr() 16.1.2.3. alt_putchar() 16.1.2.4. alt_printf()
16.2. Nios® V Processor Tools Reference x
16.2.1. Nios® V Processor Command Line Utilities 16.2.2. File Format Conversion Tools Reference 16.2.3. Other Command Line Utilities Tools Reference
16.2.1. Nios® V Processor Command Line Utilities x
16.2.1.1. niosv-shell 16.2.1.2. niosv-bsp 16.2.1.3. niosv-app 16.2.1.4. niosv-download 16.2.1.5. niosv-stack-report
16.2.2. File Format Conversion Tools Reference x
16.2.2.1. elf2hex 16.2.2.2. elf2flash
16.2.3. Other Command Line Utilities Tools Reference x
16.2.3.1. juart-terminal 16.2.3.2. cmake 16.2.3.3. make 16.2.3.4. openocd 16.2.3.5. openocd-cfg-gen
16.4. Settings Managed by Nios® V Processor Board Support Package Editor x
16.4.1. Overview of BSP Settings 16.4.2. Overview of Component and Driver Settings 16.4.3. BSP Settings Reference
16.4.2. Overview of Component and Driver Settings x
16.4.2.1. Intel FPGA Avalon-MM JTAG UART Driver Settings 16.4.2.2. Intel FPGA Avalon-MM UART Driver Settings
16.4.3. BSP Settings Reference x
16.4.3.1. Intel HAL BSP 16.4.3.2. Micrium MicroC/OS-II BSP 16.4.3.3. FreeRTOS BSP 16.4.3.4. Device Drivers BSP
16.5. Board Support Package Tcl Commands x
16.5.1. Tcl Command Environments 16.5.2. Tcl Commands for BSP Settings 16.5.3. Tcl Commands for BSP Generation Callbacks 16.5.4. Tcl Commands for Drivers and Packages
16.5.2. Tcl Commands for BSP Settings x
16.5.2.1. add_memory_device 16.5.2.2. add_memory_region 16.5.2.3. add_section_mapping 16.5.2.4. are_same_resource 16.5.2.5. delete_memory_region 16.5.2.6. delete_section_mapping 16.5.2.7. disable_sw_package 16.5.2.8. enable_sw_package 16.5.2.9. get_addr_span 16.5.2.10. get_assignment 16.5.2.11. get_available_drivers 16.5.2.12. get_available_sw_packages 16.5.2.13. get_base_addr 16.5.2.14. get_break_offset 16.5.2.15. get_break_slave_desc 16.5.2.16. get_cpu_name 16.5.2.17. get_current_memory_regions 16.5.2.18. get_current_section_mappings 16.5.2.19. get_default_memory_regions 16.5.2.20. get_driver 16.5.2.21. get_enabled_sw_packages 16.5.2.22. get_exception_offset 16.5.2.23. get_exception_slave_desc 16.5.2.24. get_fast_tlb_miss_exception_offset 16.5.2.25. get_fast_tlb_miss_exception_slave_desc 16.5.2.26. get_interrupt_controller_id 16.5.2.27. get_irq_interrupt_controller_id 16.5.2.28. get_irq_number 16.5.2.29. get_memory_region 16.5.2.30. get_module_class_name 16.5.2.31. get_module_name 16.5.2.32. get_reset_offset 16.5.2.33. get_reset_slave_desc 16.5.2.34. get_section_mapping 16.5.2.35. get_setting 16.5.2.36. get_setting_desc 16.5.2.37. get_slave_descs 16.5.2.38. is_char_device 16.5.2.39. is_connected_interrupt_controller_device 16.5.2.40. is_connected_to_data_master 16.5.2.41. is_connected_to_instruction_master 16.5.2.42. is_ethernet_mac_device 16.5.2.43. is_flash 16.5.2.44. is_memory_device 16.5.2.45. is_non_volatile_storage 16.5.2.46. is_timer_device 16.5.2.47. log_debug 16.5.2.48. log_default 16.5.2.49. log_error 16.5.2.50. log_verbose 16.5.2.51. set_driver 16.5.2.52. set_ignore_file 16.5.2.53. set_setting 16.5.2.54. update_memory_region 16.5.2.55. update_section_mapping 16.5.2.56. add_default_memory_regions 16.5.2.57. create_bsp 16.5.2.58. generate_bsp 16.5.2.59. get_available_bsp_type_versions 16.5.2.60. get_available_bsp_types 16.5.2.61. get_available_cpu_architectures 16.5.2.62. get_available_cpu_names 16.5.2.63. get_available_software 16.5.2.64. get_available_software_setting_properties 16.5.2.65. get_available_software_settings 16.5.2.66. get_bsp_version 16.5.2.67. get_cpu_architecture 16.5.2.68. get_sopcinfo_file 16.5.2.69. get_supported_bsp_types 16.5.2.70. is_bsp_hal_extension 16.5.2.71. open_bsp 16.5.2.72. save_bsp 16.5.2.73. set_bsp_version 16.5.2.74. set_logging_mode
16.5.3. Tcl Commands for BSP Generation Callbacks x
16.5.3.1. add_class_sw_setting 16.5.3.2. add_class_systemh_line 16.5.3.3. add_module_sw_property 16.5.3.4. add_module_sw_setting 16.5.3.5. add_module_systemh_line 16.5.3.6. add_systemh_line 16.5.3.7. get_class_peripheral 16.5.3.8. get_module_assignment 16.5.3.9. get_module_name 16.5.3.10. get_module_peripheral 16.5.3.11. get_module_sw_setting_value 16.5.3.12. get_peripheral_property 16.5.3.13. remove_class_systemh_line 16.5.3.14. remove_module_systemh_line 16.5.3.15. set_class_sw_setting_property 16.5.3.16. set_module_sw_setting_property
16.5.4. Tcl Commands for Drivers and Packages x
16.5.4.1. add_sw_property 16.5.4.2. add_sw_setting 16.5.4.3. add_sw_setting2 16.5.4.4. create_driver 16.5.4.5. create_os 16.5.4.6. create_sw_package 16.5.4.7. set_sw_property 16.5.4.8. set_sw_setting_property
16.6. Nios® V Processor Design Example x
16.6.1. Intel® FPGA Design Store 16.6.2. Quartus® Prime Software 16.6.3. Migrating to Other Intel® FPGA Device
16.6.2. Quartus® Prime Software x
16.6.2.1. Configurable Example Design
1. Overview of Nios® V Embedded Processor Development
2. Getting Started with the Graphical User Interface
3. Getting Started from the Command Line
4. Nios® V Processor Software Development and Implementation
5. Nios® V Processor Board Support Package Editor
6. Overview of the Hardware Abstraction Layer
7. Developing Programs Using the Hardware Abstraction Layer
8. Developing Device Drivers for the Hardware Abstraction Layer
9. Exception Handling
10. Cache and Tightly-Coupled Memory
11. MicroC/OS-II Real-Time Operating System
12. MicroC/TCP-IP Protocol Stack
13. FreeRTOS* Real-Time Operating System
14. Read-Only Zip File System
15. Publishing Component Information to Embedded Software
16. Nios® V Processor Appendix
A. Nios® V Processor Software Developer Handbook Archives
17. Revision History for the Nios® V Processor Software Developer Handbook

2.1. Using Ashling* RiscFree* IDE for Intel® FPGAs

RiscFree* is Ashling’s Eclipse CDT™ C/C++ (Development Toolkit) based on integrated development environment (IDE) for Intel® FPGAs Arm*-based HPS and RISC-V-based Nios® V processors.
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Level Two Title