Nios® V Processor Software Developer Handbook

ID 743810
Date 7/08/2024
Public
Document Table of Contents

14.3.2. Active Serial Configuration Flash in Control-block Based Devices

For Active Serial configuration flash in control-block based devices, you need to instantiate the Generic Serial Flash Interface Intel® FPGA IP in the processor system to read the file system.

During JIC generation in Convert Programming File, you can attach the HEX file system as Hex Data with the following settings:

  • Relative Addressing with specified start address (Offset from memory base address)
  • Big Endian
You can program the JIC file using the Quartus® Prime Programmer.
Figure 26. Attaching HEX File System as Convert Programming File
Note: Assume the offset from the memory base address in the BSP Editor is 0x2000000.