Nios® V Processor Software Developer Handbook

ID 743810
Date 7/08/2024
Public
Document Table of Contents

10.1. Nios® V Processor Cache Implementation

Depending on the Nios® V processor core, the processor might have data or instruction caches. You can write programs generically to function correctly on any Nios® V processor, regardless of whether it has cache memory. For a Nios® V processor without caches, cache management operations are benign and have no effect.

The details for a Nios® V processor cache are defined in the system.h file.

For example, the following processor has 4 KB instruction and data caches with 32-byte cache lines.

#define ALT_CPU_DCACHE_LINE_SIZE 32

#define ALT_CPU_DCACHE_SIZE 4096

#define ALT_CPU_ICACHE_LINE_SIZE 32

#define ALT_CPU_ICACHE_SIZE 4096

The HAL application program interface (API) provides the following functions for managing cache memory:

  • alt_dcache_flush()
  • alt_dcache_flush_no_writeback()
  • alt_dcache_flush_all()
  • alt_icache_flush()
  • alt_icache_flush_all()