F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

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ID 720989
Date 2/23/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide 2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters 6. Interface Signals 7. Configuration Registers A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Device Speed Grade Support 2.5. Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Specifying the IP Core Parameters and Options 3.4. Generated File Structure 3.5. Simulating Intel® FPGA IP Cores 3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 3.7. Integrating Your IP Core in Your Design
3.2. Installing and Licensing Intel® FPGA IP Cores x
3.2.1. Intel® FPGA IP Evaluation Mode
3.7. Integrating Your IP Core in Your Design x
3.7.1. Adding the F-tile Reference and System PLL IP
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed 4.4. IEEE 802.3 Clause 37 Auto-Negotiation 4.5. USXGMII
4.1. Clocking and Reset Sequence x
4.1.1. Clocking 4.1.2. Reset
6. Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. Serial Interface Signals 6.4. Avalon® Memory-Mapped Interface Signals 6.5. XGMII Signals 6.6. Transceiver Status and Transceiver Clock Status Signals 6.7. Reconfiguration Signals 6.8. Operating Speed and Status Signals
7. Configuration Registers x
7.1. Register Map 7.2. PHY Registers
1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

6.5. XGMII Signals

Table 19.  XGMII Signals
Signal Name Direction Width Description
XGMII Transmit—synchronous to xgmii_tx_coreclkin
xgmii_tx_control Input 4 TX control from the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration.

The xgmii_tx_control bit corresponds to the xgmii_tx_data bits. For example, xgmii_tx_control[0] corresponds to xgmii_tx_data[7:0], xgmii_tx_control[1] corresponds to xgmii_tx_data[15:8], and so on.

xgmii_tx_data Input 32 TX data from the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration.

The MAC sends the data in the following order: bits [7:0], bits [15:8], bit [23:16], and so on.
xgmii_tx_valid Output 1 Indicates valid data on xgmii_tx_control and xgmii_tx_data from the MAC.
Your logic/MAC must toggle the valid data as shown below:
Speed Toggle Rate
10M Asserted once every 1000 clock cycles
100M Asserted once every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted on every clock cycle
XGMII Receive—synchronous to xgmii_rx_coreclkin
xgmii_rx_control Output 4 RX control to the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration.

The xgmii_rx_control bit corresponds to the xgmii_rx_data bits. For example, xgmii_rx_control[0] corresponds to xgmii_rx_data[7:0], xgmii_rx_control[1] corresponds to xgmii_rx_data[15:8], and so on.

xgmii_rx_data Output 32 RX data to the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration.

The PHY sends the data in the following order: bits [7:0], bits [15:8], bit [23:16], and so on.
xgmii_rx_valid Output 1 Indicates valid data on xgmii_rx_control and xgmii_rx_data from the MAC.
The toggle rate from the PHY is shown in the table below.
Speed Toggle Rate
10M Asserted once every 1000 clock cycles
100M Asserted once every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted on every clock cycle
Note: The toggle rate may vary when the start of a packet is received or when rate match occurs inside the PHY. You should not expect the valid data pattern to be fixed.
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