F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 2/23/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.2. Reset

You can connect the reset, tx_digitalreset, and rx_digitalreset signals with inverted polarity to the i_rst_n, i_tx_rst_n, and i_rx_rst_n signals respectively.

Refer to Reset Sequence in F-Tile Ethernet Intel FPGA Hard IP User Guide for reset sequence of the i_rst_n, i_tx_rst_n, i_rx_rst_n, and i_reconfig_reset signals.