F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 2/23/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.4. Avalon® Memory-Mapped Interface Signals

The Avalon memory-mapped interface is an Avalon memory-mapped slave port. This interface uses word addressing and provides access to the 32-bit configuration registers of the PHY in Table 25. The following signals are synchronous to csr_clk.

Table 18.   Avalon® Memory-Mapped Interface Signals
Signal Name Direction Width Description
Avalon® Memory-Mapped CSR
csr_address Input 11 Use this bus to specify the register address to read from or write to.
csr_write Input 1 Assert this signal to request a write operation.
csr_read Input 1 Assert this signal to request a read operation.
csr_writedata Input 32 Data to be written to the specified register. The data is written only when the csr_waitrequest signal is deasserted.
csr_readdata Output 32 Data read from the specified register. The data is valid only when the csr_waitrequest signal is deasserted.
csr_waitrequest Output 1 When asserted, indicates that the PHY is busy and not ready to accept any read or write requests.
  • When you have requested for a read or write, keep the control signals to the Avalon® memory-mapped interface constant while this signal is asserted. The request is complete when it is deasserted.
  • This signal can be high or low during idle cycles and reset. Therefore, the user application must not make any assumption of its assertion state during these periods.