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1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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6.4. Avalon® Memory-Mapped Interface Signals
The Avalon memory-mapped interface is an Avalon memory-mapped slave port. This interface uses word addressing and provides access to the 32-bit configuration registers of the PHY in Table 25. The following signals are synchronous to csr_clk.
Signal Name | Direction | Width | Description |
---|---|---|---|
Avalon® Memory-Mapped CSR | |||
csr_address | Input | 11 | Use this bus to specify the register address to read from or write to. |
csr_write | Input | 1 | Assert this signal to request a write operation. |
csr_read | Input | 1 | Assert this signal to request a read operation. |
csr_writedata | Input | 32 | Data to be written to the specified register. The data is written only when the csr_waitrequest signal is deasserted. |
csr_readdata | Output | 32 | Data read from the specified register. The data is valid only when the csr_waitrequest signal is deasserted. |
csr_waitrequest | Output | 1 | When asserted, indicates that the PHY is busy and not ready to accept any read or write requests.
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