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1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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4.4. IEEE 802.3 Clause 37 Auto-Negotiation
This module receives 32-bit XGMII with data valid from RX 64/32 width adaptor at 322.265625 MHz, and output 32-bit auto-negotiation data in a format shown in the following table at 312.5 MHz. The received XGMII data are decoded to extract the auto-negotiation config words from auto-negotiation message. The received AN config words are processed by the auto-negotiation engine described in IEEE 802.3 Clause 37.
Lane | XGMII Control | XGMII Data |
---|---|---|
0 | 0x1 | 0x9C |
1 | 0x0 | Config [15:8] |
2 | 0x0 | Config [7:0] |
3 | 0x0 | Auto-Neg Opcode (Cisco) 0x03 |