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1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
You can select the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core for Intel® Agilex™ F-tile devices from the Intel® Quartus® Prime Pro Edition IP catalog. To customize the PHY IP core, specify the parameters in the IP parameter editor.
Figure 9. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Parameter Editor
Parameter | Options | Description |
---|---|---|
External PHY | ||
Connect to NBASE-T PHY | On | This parameter is enabled by default as only 10M/100M/1G/2.5G/5G/10G (USXGMII) mode is supported and the external PHY must be NBASE-T compatible. |
PHY Options | ||
Speed | 10M/100M/1G/2.5G/5G/10G (USXGMII) |
The operating speed of the PHY. |
Transceiver Options | ||
PMA reference frequency | 156.250000 312.500000 322.265625 |
Specify the frequency of the reference clock to PMA from system PLL (i_clk_ref). |