F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 2/23/2022
Public

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2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview

The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core for Intel® Agilex™ devices (F-tile) implements the Ethernet protocol as defined in the IEEE 802.3 2005 Standard. It consists of a physical coding sublayer (PCS) function and an embedded physical media attachment (PMA). You can dynamically switch the PHY operating speed. The IP leverages F-tile Ethernet hard IP transceiver for serial transmission with soft logic added to implement interface to MAC.
Note: Intel® FPGAs implement and support the required Media Access Control (MAC), PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external NBASE-T PHY standard devices. You are required to use an external PHY device to drive any copper media.