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1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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2.5. Resource Utilization
The following estimates are obtained by compiling the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP for Intel® Agilex™ AGIB027R31B1E2VR0 device using Intel® Quartus® Prime Pro Edition software.
Speed | ALMs | ALUTs | Logic Registers | Memory Block (M20K) |
---|---|---|---|---|
10M/100M/1G/2.5G/5G/10G (USXGMII) | 1028 | 1480 | 2266 | 3 |