F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 2/23/2022
Public

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6.3. Serial Interface Signals

Table 17.  Serial Interface Signals
Signal Name Direction Width Description
serial_o_tx_serial Output 1 Transmit serial data lanes.
serial_o_tx_serial_n Output 1
serial_i_rx_serial Input 1 Receive serial data lanes.
serial_i_rx_serial_n Input 1