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1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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3. Getting Started
The following section explains how to install, parameterize, simulate, and initialize the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core.
Section Content
Introduction to Intel FPGA IP Cores
Installing and Licensing Intel FPGA IP Cores
Specifying the IP Core Parameters and Options
Generated File Structure
Simulating Intel FPGA IP Cores
Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core
Integrating Your IP Core in Your Design