F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 2/23/2022
Public

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4.1.1. Clocking

Figure 8. Clocking Diagram

The ref_clk signal is the reference clock to the F-tile Reference and System PLL Clocks Intel® FPGA IP which must be connected to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP. Intel recommends that you use 156.25 Mhz for ref_clk. Please refer to Table 15 for more details on clock signals.