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1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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6.6. Transceiver Status and Transceiver Clock Status Signals
Signal Name | Direction | Width | Description |
---|---|---|---|
Transceiver Status Signals | |||
o_tx_lanes_stable | Output | 1 | Active-high asynchronous status signal for the TX datapath.
|
o_rx_pcs_ready | Output | 1 | Active-high asynchronous status signal for the RX datapath.
|
o_rx_block_lock | Output | 1 | Asserted when the 66b block alignment is finished on all PCS virtual lanes. |
Transceiver Clock Status Signals | |||
o_sys_pll_locked | Output | 1 | Indicates that the system PLL is locked. Do not use o_clk_pll until o_sys_pll_locked is high. |
o_tx_pll_locked | Output | 1 | Indicates that the TX serdes PLLs are locked. |
o_cdr_lock | Output | 1 | Indicates that the recovered clocks are locked to RX data. |