F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 2/23/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.6. Transceiver Status and Transceiver Clock Status Signals

Table 20.  Transceiver Status and Transceiver Clock Status Signals
Signal Name Direction Width Description
Transceiver Status Signals
o_tx_lanes_stable Output 1 Active-high asynchronous status signal for the TX datapath.
  • Asserts when the TX datapath is ready to send data.
  • Deasserts when the i_tx_rst_n or i_rst_n signal asserts.
o_rx_pcs_ready Output 1 Active-high asynchronous status signal for the RX datapath.
  • Asserts when the RX datapath is ready to receive data.
  • Deasserts when the i_rx_rst_n or i_rst_n signal asserts.
o_rx_block_lock Output 1 Asserted when the 66b block alignment is finished on all PCS virtual lanes.
Transceiver Clock Status Signals
o_sys_pll_locked Output 1 Indicates that the system PLL is locked.

Do not use o_clk_pll until o_sys_pll_locked is high.

o_tx_pll_locked Output 1 Indicates that the TX serdes PLLs are locked.
o_cdr_lock Output 1 Indicates that the recovered clocks are locked to RX data.