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1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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2.2. Features
Feature | Description |
---|---|
Operating speeds | 10M, 100M, 1G, 2.5G, 5G, and 10G. |
MAC-side interface | 32-bit XGMII for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T). |
Network-side interface | 10.3125 Gbps for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T). |
Avalon® Memory-Mapped ( Avalon® -MM) interface | Provides access to the configuration registers of the PHY. |
Physical Coding Sublayer (PCS) function | USXGMII PCS for 10M/100M/1G/2.5G/5G/10G (USXGMII). |
Auto-negotiation | USXGMII Auto-negotiation supported in the 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T) configuration. |