F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

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ID 720989
Date 2/23/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide 2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters 6. Interface Signals 7. Configuration Registers A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Device Speed Grade Support 2.5. Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Specifying the IP Core Parameters and Options 3.4. Generated File Structure 3.5. Simulating Intel® FPGA IP Cores 3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 3.7. Integrating Your IP Core in Your Design
3.2. Installing and Licensing Intel® FPGA IP Cores x
3.2.1. Intel® FPGA IP Evaluation Mode
3.7. Integrating Your IP Core in Your Design x
3.7.1. Adding the F-tile Reference and System PLL IP
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed 4.4. IEEE 802.3 Clause 37 Auto-Negotiation 4.5. USXGMII
4.1. Clocking and Reset Sequence x
4.1.1. Clocking 4.1.2. Reset
6. Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. Serial Interface Signals 6.4. Avalon® Memory-Mapped Interface Signals 6.5. XGMII Signals 6.6. Transceiver Status and Transceiver Clock Status Signals 6.7. Reconfiguration Signals 6.8. Operating Speed and Status Signals
7. Configuration Registers x
7.1. Register Map 7.2. PHY Registers
1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

6.2. Reset Signals

Table 16.   Reset Signals
Signal Name Direction Width Description
reset Input 1 Active-high global reset. Assert this signal to trigger an asynchronous global reset.
tx_digitalreset Input 1 Active-high signal. When asserted, triggers an asynchronous reset to the digital logic on the TX path.
rx_digitalreset Input 1 Active-high signal. When asserted, triggers an asynchronous reset to the digital logic on the RX path.
i_reconfig_reset Input 1 Active-high reconfiguration reset signal. Reset the entire reconfiguration clock domain, including the soft registers (CSRs). You must assert this reset after power-on or during the configuration. The i_reconfig_clk signal must be stable before deasserting this reset.
i_rst_n Input 1

Active-low asynchronous reset signal. Do not deassert until o_rst_ack_n deasserts.

  • Resets the TX interface, including the TX PCS.
  • Resets the RX interface, including the RX PCS.
  • Resets the TX PMA and TX EMIB.
  • Resets the RX PMA and RX EMIB.

This reset leads to assertion of the o_rst_ack_n output signal.

o_rst_ack_n Output 1 Active-low asynchronous acknowledgment signal for the i_rst_n reset.

Do not deassert the i_rst_n reset until the o_rst_ack_n asserts.

i_tx_rst_n Input 1 Active-low asynchronous reset signal.

Resets the entire TX datapath, including the TX PCS, TX PMA, and TX EMIB. Do not deassert until the o_tx_rst_ack_n asserts.

o_tx_rst_ack_n Output 1 Active-low asynchronous acknowledgment signal for the i_tx_rst_n reset.

Do not deassert the i_tx_rst_n reset until o_tx_rst_ack_n asserts.

i_rx_rst_n Input 1 Active-low asynchronous reset signal.

Resets the entire RX datapath, including the RX PCS, RX PMA, and RX EMIB. Do not deassert until o_rx_rst_ack_n asserts.

o_rx_rst_ack_n Output 1 Active-low asynchronous acknowledgment signal for the i_rx_rst_n reset.

Do not deassert the i_rx_rst_n reset until o_rx_rst_ack_n asserts.

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