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1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
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4.5. USXGMII
The F-tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core implements USXGMII PCS based on Cisco specification.
This PCS can interface with external NBASE-T PHY. It supports 10M/100M/1G/2.5G/5G/10G speeds based on packet data replication.
The USXGMII PCS supports the following features:
- 10G-USXGMII – 10M/100M/1G/2.5G/5G/10G speeds
- Full duplex only
- USXGMII Auto-Negotiation