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2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
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Ixiasoft
2.4.1. Setting Up Software Development Environment for Windows
- Install the GNU make utility on your Windows development machine.
Note: Intel® used the GNU make utility version 3.81a to build the software in the Stratix® V Network Reference Platform.
- Install Microsoft Visual Studio.
Note: Microsoft Visual Studio 2008 (9.0) was used to build the software in s5_net.
- Set up the software development environment so that the Intel® FPGA SDK for OpenCL™ user can invoke SDK commands and utilities at a command prompt.
- Modify the <your_custom_platform_name>/source/Makefile.common file so that TOP_DEST_DIR points to the top-level directory of your Custom Platform.
- In the Makefile.common file, set the JUNGO_LICENSE variable to your Jungo WinDriver license.
For information on how to acquire a Jungo Windriver license, visit the Jungo Connectivity Ltd. website.
- To check that you have set up the software development environment properly, invoke the gmake or gmake clean command.
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