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2.1. Initializing Your Custom Platform
2.2. Removing Unused Hardware
2.3. Integrating Your Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Software Development Environment
2.5. Building the Software in Your Custom Platform
2.6. Establishing Host Communication
2.7. Connecting the Memory
2.8. Integrating an OpenCL Kernel
2.9. Programming Your FPGA Quickly Using CvP
2.10. Guaranteeing Timing Closure
2.11. Troubleshooting
3.1. Host-FPGA Communication over PCIe
3.2. DDR3 as Global Memory for OpenCL Applications
3.3. QDRII as Heterogeneous Memory for OpenCL Applications
3.4. Host Connection to OpenCL Kernels
3.5. Implementation of UDP Cores as OpenCL Channels
3.6. FPGA System Design
3.7. Guaranteed Timing Closure
3.8. Addition of Timing Constraints
3.9. Connection to the Intel® FPGA SDK for OpenCL™
3.10. FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. OpenCL Utilities Implementation
3.13. Stratix V Network Reference Platform Implementation Considerations
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1.1.1. Legacy Board Support
The Intel® FPGA SDK for OpenCL™ attempts to automigrate your existing Custom Platform to the most recent Intel® Quartus® Prime Design Suite version.
Refer to the Custom Platform Automigration for Forward Compatibility section in the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide for more information and instructions.
The Custom Platform Toolkit is available in the SDK's board directory (that is, INTELFPGAOCLSDKROOT/board/custom_platform_toolkit).
CAUTION:
The Stratix® V Network Reference Platform and the Stratix V Network Reference Platform Porting Guide are not compatible with Custom Platforms created prior to Altera SDK for OpenCL version 14.0.
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