Visible to Intel only — GUID: mwh1409959034260
Ixiasoft
Visible to Intel only — GUID: mwh1409959034260
Ixiasoft
6.15.16. Avalon® Tri-State Agent Interface Signal Types
Name | Width | Direction | Required | Description |
---|---|---|---|---|
address |
1 - 32 | input | No |
Address lines to the agent port. Specifies a byte offset into the agent’s address space. |
read read_n |
1 | input | No |
Read-request signal. Not required if the agent port never outputs data. If present, data must also be used. |
write write_n |
1 | input | No |
Write-request signal. Not required if the agent port never receives data from a host. If present, data must also be present, and writebyteenable cannot be present. |
chipselect chipselect_n |
1 | input | No |
When present, the agent port ignores all Avalon® memory mapped signals unless chipselect is asserted. chipselect is always present in combination with read or write |
outputenable outputenable_n |
1 | input | Yes |
Output-enable signal. When deasserted, a tri-state agent port must not drive its data lines otherwise data contention may occur. |
data |
8,16, 32, 64, 128, 256, 512, 1024 | bidir | No |
Bidirectional data. During write transfers, the FPGA drives the data lines. During read transfers the agent device drives the data lines, and the FPGA captures the data signals and provides them to the host. |
byteenable byteenable_n |
2, 4, 8,16, 32, 64, 128 | input | No |
Enables specific byte lanes during transfers. Each bit in byteenable corresponds to a byte lane in data. During writes, byteenables specify which bytes the host is writing to the agent. During reads, byteenables indicates which bytes the host is reading. Agents that simply return data with no side effects are free to ignore byteenables during reads. When more than one byte lane is asserted, all asserted lanes are guaranteed to be adjacent. The number of adjacent lines must be a power of 2, and the specified bytes must be aligned on an address boundary for the size of the data. The following are legal values for a 32-bit agent: |
writebyteenable writebyteenable_n |
2,4,8,16, 32, 64,128 | input | No |
Equivalent to the logical AND of the byteenable and write signals. When used, the write signal is not used. |
begintransfer1 |
1 | input | No |
Asserted for the first cycle of each transfer. |
Note: All Avalon® signals are active high. Avalon® signals that can also be asserted low list both versions in the Signal Role column.
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